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Dive into the research topics where Kailash Chandra Ray is active.

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Featured researches published by Kailash Chandra Ray.


IEEE Transactions on Instrumentation and Measurement | 2017

ECG Signal Analysis Using DCT-Based DOST and PSO Optimized SVM

Sandeep Raj; Kailash Chandra Ray

Signal processing techniques are an obvious choice for real-time analysis of electrocardiography (ECG) signals. However, classical signal processing techniques are unable to deal with the nonstationary nature of the ECG signal. In this context, this paper presents a new approach, i.e., discrete orthogonal stockwell transform using discrete cosine transform for efficient representation of the ECG signal in time–frequency space. These time–frequency features are further reduced in lower dimensional space using principal component analysis, representing the morphological characteristics of the ECG signal. In addition, the dynamic features (i.e., RR-interval information) are computed and concatenated to the morphological features to constitute the final feature set, which is utilized to classify the ECG signals using support vector machine (SVM). In order to improve the classification performance, particle swarm optimization technique is employed for gradually tuning the learning parameters of the SVM classifier. In this paper, ECG data exhibiting 16 classes of the most frequently occurring arrhythmic events are taken from the benchmark MIT-BIH arrhythmia database for the validation of the proposed methodology. The experimental results yielded an improved overall accuracy, sensitivity (Sp), and positive predictivity (Pp) of 98.82% in comparison with the existing approaches available in the literature.


IEEE Transactions on Computers | 2014

Low Latency Hybrid CORDIC Algorithm

Rohit Shukla; Kailash Chandra Ray

CORDIC (COordinate Rotational DIgital Computer) has gained momentum for decades because of its less hardware complexity in real time applications such as communication systems, signal and image processing. The main drawbacks of CORDIC algorithm are increased number of iterations, scale factor calculation and compensation. Researchers have worked to reduce the latency in terms of number of iterations and minimize the critical path with redundant arithmetic and fast adders. Some researchers have proposed algorithms to reduce the number of iterations to \mbin/2 plus additional iterations including rotation and scale factor calculation and compensation for \mbin bit precision. However, to the knowledge of the authors, no further reduction of number of iterations has been addressed. In this context, the authors have proposed a new hybrid CORDIC algorithm which reduces the iteration to (3\mbin/8) + 1 for \mbin bit precision including the scale factor calculation and compensation. The proposed algorithm and its first order architecture have been compared with the existing low latency CORDIC algorithms in terms of iterations, hardware complexity and critical delay. The scope of this work is to present a novel hybrid CORDIC algorithm along with first order hardware architecture.


Microprocessors and Microsystems | 2015

ARM-based arrhythmia beat monitoring system

Sandeep Raj; G.S.S. Praveen Chand; Kailash Chandra Ray

This paper aims for accurate diagnosis of arrhythmia beats in real time to enhance the health care service for cardiovascular diseases. The proposed methodology for the diagnosis involves the integration of the R-peak detection algorithm, FFT (fast fourier transform) based discrete wavelet transform for feature extraction and feedforward based Neural Network Architecture to classify generic cardiac beat classes into eight categories namely Right Bundled Block, Left Bundled Block, Preventricular Contraction (PVC), Atrial Premature Contraction (APC), Ventricular Flutter wave (VF), Paced Beat, Ventricular Escape (VE) and Normal beat. The paper contributes the development, prototyping and analysis of proposed methodology on ARM (Advanced RISC Machine) based SoC (System-on-Chip) in laboratory setup. This system is validated by generating real-time ECG signals using MIT-BIH database while the output of the system is monitored on the displaying device. The performance analysis of the proposed methodology implemented on the microcontroller based system is computed by performing the experiment which achieves a high overall accuracy of 97.4% with average sensitivity ( S e ) of 97.57%, specificity ( S p ) of 99.59% and positive predictivity ( P p ) of 97.93%. The system provides an assistive diagnostic solution to the users to lead a healthy lifestyle. Moreover, the ARM-based system can be fabricated into a handheld device for reliable automatic monitoring of the condition of heart by patients.


Computer Methods and Programs in Biomedicine | 2016

Cardiac arrhythmia beat classification using DOST and PSO tuned SVM

Sandeep Raj; Kailash Chandra Ray; Om Shankar

BACKGROUND AND OBJECTIVE The increase in the number of deaths due to cardiovascular diseases (CVDs) has gained significant attention from the study of electrocardiogram (ECG) signals. These ECG signals are studied by the experienced cardiologist for accurate and proper diagnosis, but it becomes difficult and time-consuming for long-term recordings. Various signal processing techniques are studied to analyze the ECG signal, but they bear limitations due to the non-stationary behavior of ECG signals. Hence, this study aims to improve the classification accuracy rate and provide an automated diagnostic solution for the detection of cardiac arrhythmias. METHODS The proposed methodology consists of four stages, i.e. filtering, R-peak detection, feature extraction and classification stages. In this study, Wavelet based approach is used to filter the raw ECG signal, whereas Pan-Tompkins algorithm is used for detecting the R-peak inside the ECG signal. In the feature extraction stage, discrete orthogonal Stockwell transform (DOST) approach is presented for an efficient time-frequency representation (i.e. morphological descriptors) of a time domain signal and retains the absolute phase information to distinguish the various non-stationary behavior ECG signals. Moreover, these morphological descriptors are further reduced in lower dimensional space by using principal component analysis and combined with the dynamic features (i.e based on RR-interval of the ECG signals) of the input signal. This combination of two different kinds of descriptors represents each feature set of an input signal that is utilized for classification into subsequent categories by employing PSO tuned support vector machines (SVM). RESULTS The proposed methodology is validated on the baseline MIT-BIH arrhythmia database and evaluated under two assessment schemes, yielding an improved overall accuracy of 99.18% for sixteen classes in the category-based and 89.10% for five classes (mapped according to AAMI standard) in the patient-based assessment scheme respectively to the state-of-art diagnosis. The results reported are further compared to the existing methodologies in literature. CONCLUSIONS The proposed feature representation of cardiac signals based on symmetrical features along with PSO based optimization technique for the SVM classifier reported an improved classification accuracy in both the assessment schemes evaluated on the benchmark MIT-BIH arrhythmia database and hence can be utilized for automated computer-aided diagnosis of cardiac arrhythmia beats.


international conference on signal processing | 2010

FPGA implementation of discrete fractional Fourier transform

M. V. N. V. Prasad; Kailash Chandra Ray; Anindya Sundar Dhar

Since decades, fractional Fourier transform has taken a considerable attention for various applications in signal and image processing domain. On the evolution of fractional Fourier transform and its discrete form, the real time computation of discrete fractional Fourier transform is essential in those applications. On this context, we have proposed new hardware architecture for implementing a Discrete Fractional Fourier Transform (DFrFT) which requires hardware complexity of O(4N), where N is transform order. This proposed architecture has been simulated and synthesized using verilogHDL, targeting a FPGA device (XLV5LX110T). The simulation results are very close to the results obtained by using MATLAB. The result shows that, this architecture can be operated on a maximum frequency of 217MHz.


design and diagnostics of electronic circuits and systems | 2011

Hardware efficient design of Variable Length FFT Processor

Vinay Kumar Gautam; Kailash Chandra Ray; Pauline C. Haddow

Proliferation of handheld devices and growing interests in pervasive computing has led to the need for more flexible communication solutions where a single device integrates various wired and wireless communication standards e.g. Asymmetric Digital Subscriber loop (ADSL), Very high speed Digital Subscriber Loop (VDSL), Digital Audio Broadcasting (DAB), Digital Video Broadcasting (DVB-T/H) and 802.11. In this paper, such a flexible communication solution is presented, applicable to all useful FFT processor lengths: 2n (n=6, 7…13) and implemented on a flexible platform: Field Programmable Gate Array (FPGA). The solution is optimized ensuring an efficient implementation with respect to resource usage whilst ensuring that the solution meets the throughput requirements of the individual standards. The key features of the efficient design include: a conflict free in-place memory replacement scheme for intermediate data storage; a dynamic address generator scheme and the CORDIC (CO-ordinate Rotational Digital Computer) technique for twiddle factor multiplication.


Iet Signal Processing | 2016

Efficient methodology for electrocardiogram beat classification

Kailash Chandra Ray; Piyush Sharma

Electrocardiogram (ECG) beat behaves as a non-linear and non-stationary signal. Since most of the existing data processing tools are poor alternatives for processing such signals, Hilbert–Huang transform (HHT) proves to be an efficient method as it deals with a time-varying frequency spectrum. In this study, a new and efficient methodology is proposed using HHT for feature selection which includes a set of essential features such as weighted mean frequency, Kolmogorov complexity and other statistical features (median, standard deviation, kurtosis, skewness and central moment) computed from the intrinsic mode functions extracted using the empirical mode decomposition (EMD) algorithm. Further, one-against-one multi-class support vector machine is employed for the classification of six generic ECG beats, namely: normal, left bundle branch block, right bundle branch block, premature ventricular contraction, paced beat and atrial premature beat. The classification process in this study yields better results than existing methodologies in terms of classification accuracy equal to 99.51% along with sensitivity, specificity and positive predictivity of 98.64, 99.77 and 98.17%, respectively.


international conference on power, control and embedded systems | 2010

FPGA implementation of fast FIR low pass filter for EMG removal from ECG signal

Rakesh Chand; Pawan Tripathi; Abhishek Mathur; Kailash Chandra Ray

This paper presents the hardware implementation of fast FIR low pass filter for Electromyogram (EMG) removal from Electrocardiogram (ECG) signal. We designed the architecture having less critical delay then convention FIR design and fast enough to remove EMG from ECG signal. We Proposed branched tree architecture for adder connection to reduce the critical delay. The Proposed architecture has been implemented on FPGA using Verilog Hardware Description Language (HDL). Since coefficient quantization technique is used, so this implementation consumes lesser area that reduces the Hardware consumption. We have used target device Virtex-5 (“xc5vlx110t-2-ff1136”), which is a preferred device in the field for modern Digital Signal Processing (DSP) applications.


Journal of Computers | 2008

High Throughput VLSI Architecture for Blackman Windowing in Real Time Spectral Analysis

Kailash Chandra Ray; Anindya Sundar Dhar

This paper presents a high throughput VLSI architecture for Blackman windowing. Since most of the implementation of windowing functions for real time applications, are based on either ROM or DSP processor. Here the proposed architecture is designed using major blocks like CORDIC(CO-ordinate Rotation DIgital Computer) and Han-Carlson adder. This architecture is flexible in terms of window length. So that a single chip can be used for those applications, where variable length is required. The synthesized result of 16-bit word size architecture with commercially available 0.18µm CMOS technology using Synopsys Design Analyzer, shows that the throughput of this architecture is 400Msamples/s with core area of 21mm2 .


Expert Systems With Applications | 2018

Sparse representation of ECG signals for automated recognition of cardiac arrhythmias

Sandeep Raj; Kailash Chandra Ray

Abstract As per the report of the World Health Organization (WHO), the mortalities due to cardiovascular diseases (CVDs) have increased to 50 million worldwide. Therefore, it is essential to have an efficient diagnosis of CVDs to enhance the healthcare in the clinical cardiovascular domain. The ECG signal analysis of a patient is a very popular tool to perform diagnosis of CVDs. However, due to the non-stationary nature of ECG signal and higher computational burden of the existing signal processing methods, the automated and efficient diagnosis remains a challenge. This paper presents a new feature extraction method using the sparse representation technique to efficiently represent the different ECG signals for efficient analysis. The sparse method decomposes an ECG signal into elementary waves using an overcomplete gabor dictionary. Four features such as time delay, frequency, width parameter, and square of expansion coefficient are extracted from each of the significant atoms of the dictionary. These features are concatenated and analyzed to determine the optimal length of discriminative feature vector representing each of the ECG signal. These extracted features representing the ECG signals are further classified using machine learning techniques such as least-square twin SVM, k-NN, PNN, and RBFNN. Further, the learning parameters of the classifiers are optimized using ABC and PSO techniques. The experiments are carried out for the proposed methods (i.e. feature extraction along with all classifiers) using benchmark MIT-BIH data and evaluated under category and personalized analysis schemes. Experimental results show that the proposed ECG signal representation using sparse decomposition technique with PSO optimized least-square twin SVM (best classifier model among k-NN, PNN and RBFNN) reported higher classification accuracy of 99.11% in category and 89.93% in personalized schemes respectively than the existing methods to the state-of-art diagnosis.

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Anindya Sundar Dhar

Indian Institute of Technology Kharagpur

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Sandeep Raj

Indian Institute of Technology Patna

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K.K. Soundra Pandian

Indian Institute of Technology Patna

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Preetam Kumar

Indian Institute of Technology Patna

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Vikas Kumar

Indian Institute of Technology Patna

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Rakesh Palisetty

Indian Institute of Technology Patna

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Abhishek Mathur

Indian Institute of Information Technology

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Pawan Tripathi

Indian Institute of Information Technology

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Rakesh Chand

Indian Institute of Information Technology

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Saptadeep Pal

Indian Institute of Technology Patna

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