Anindya Sundar Dhar

Optical properties of RF sputtered strontium substituted barium titanate thin films

Abstract Optically active strontium substituted barium titanate (Ba x Sr 1− x TiO 3 ) thin films have been prepared on p-silicon and glass (Corning 7059) substrates by RF magnetron sputtering in a flowing Ar/O 2 atmosphere. Transmittance and ellipsometric study of the films show that the refractive index is a function of the film composition. In the UV-visible transmittance spectra, the band edge absorption of BST films shifts to lower energies when the material is in the crystalline state rather than the amorphous state. Optical band gap calculated from UV-visible transmittance spectra increases with the increasing strontium concentration. Extinction coefficient of the films in visible region is in the order of 10 −3 . The infrared (IR) spectra with dominant absorption bands due to Ti O stretching, Ti O bending and (cation) TiO 3 vibrations suggest the formation of a single-phasic perovskite BST film in magnetron sputtering.

An array architecture for fast computation of discrete Hartley transform

Fast computation of the discrete Hartley transform (DHT) may be performed by employing a set of linear arrays of Givens rotors. It is shown that the interconnections between the linear arrays can be realized in a regular fashion governed by a permutation cycle that can be determined by simple arithmetic involving a primitive root of the transform length. A suitable implementation of the Givens rotor with add/subtract units and hard-wired shifters is also suggested. >

FPGA realization of a CORDIC based FFT processor for biomedical signal processing

Abstract In this paper, the design of a CORDIC algorithm based FFT processor is presented which is primarily intended to be used in biomedical signal processing. The processor is implemented in a field programmable gate array (FPGA) that is a very cost effective option for low design cycle desktop testing, and its performance is found to be satisfactory. The choice of the CORDIC algorithm for realizing the basic butterfly operation for the FFT saves a lot of hardware compared to its counterparts employing other techniques. The address generation unit required for fetching data from and writing results into the memory in proper sequence, is also incorporated within the chip which houses the controller as well. The full design is implemented using Xilinx XC 4025 series FPGA requiring approximately 750 configurable logic blocks.

Nonvolatile and unipolar resistive switching characteristics of pulsed laser ablated NiO films

Unipolar nonvolatile resistive switching memory properties of pulse laser ablated nickel oxide films have been studied. Grazing incidence x-ray diffraction and electron diffraction spectra of the oxide films reveal polycrystalline nature of deposited NiO films. Cross-sectional transmission electron micrograph shows a fairly uniform oxide surface. The rms surface roughnesses of deposited oxides have been studied as a function of annealing temperature using atomic force microscopy. By applying a proper voltage bias and compliance, Pt/NiO/Pt structures exhibited unipolar resistive switching having a very low SET and RESET voltages. The OFF state resistance and SET voltage are found to increase with the increase in annealing temperature. The ratio between the two resistance states can be as high as 1000. The current conduction phenomena at two resistance states have been studied. The switching phenomena have been explained using the rupture and formation of conducting filaments. The effect of postdeposition a...

CORDIC architectures: a survey

In the last decade, CORDIC algorithm has drawn wide attention from academia and industry for various applications such as DSP, biomedical signal processing, software defined radio, neural networks, and MIMO systems to mention just a few. It is an iterative algorithm, requiring simple shift and addition operations, for hardware realization of basic elementary functions. Since CORDIC is used as a building block in various single chip solutions, the critical aspects to be considered are high speed, low power, and low area, for achieving reasonable overall performance. In this paper, we first classify the CORDIC algorithm based on the number system and discuss its importance in the implementation of CORDIC algorithm. Then, we present systematic and comprehensive taxonomy of rotational CORDIC algorithms, which are subsequently discussed in depth. Special attention has been devoted to the higher radix and flat techniques proposed in the literature for reducing the latency. Finally, detailed comparison of various algorithms is presented, which can provide a first-order information to designers looking for either further improvement of performance or selection of rotational CORDIC for a specific application.

Optical and dielectric properties of junctionlike CdS nanocomposites embedded in polymer matrix

CdS nanocomposites have been grown in a polymer (polyvinyl alcohol) matrix using a simple chemical bath deposition process. Transmission electron micrographs of nanocomposites grown at different solution temperatures revealed the formation of isolated as well as junctionlike structures. X-ray and selected area electron diffraction patterns show that the nanocomposites are polycrystalline with cubic CdS phase. Optical band gaps of nanocomposite films are found to decrease (3.26–2.86eV) with the increase in bath temperature from 70to90°C. Photoluminescence spectra show strong green emission attributed to the Cd2+ or Cd+ ion-related recombination via moderately deep trap states. The nanocomposites show an enormous enhancement of dielectric constant in polyvinyl alcohol matrix over a frequency range of 40Hz–10MHz.

Electroluminescence and charge storage characteristics of quantum confined germanium nanocrystals

Quantum confined Ge nanocrystals embedded in high bandgap and high-k Al2O3 dielectric matrix have been synthesized to demonstrate dual functional devices using Si-compatible fabrication technology. Transmission electron microscopy has shown the formation of Ge nanocrystals of varying diameter from 2.5 to 7.5 nm, much lower than the excitonic Bohr radius of Ge. A broad visible electroluminescence band at room temperature has been observed, which is attributed to the recombination of injected electrons and holes in Ge nanocrystals. An anti-clockwise hysteresis in the capacitance-voltage measurement of these devices indicates the charge storage in nanocrystals, useful for floating gate memory devices.

RF magnetron sputtered high-k barium strontium titanate thin films on magnetoresistive La0.7Ca0.3MnO3 electrode

Abstract Ba x Sr 1− x TiO 3 (BST) thin films have been deposited by rf magnetron sputtering on multi-layered perovskite conducting bottom electrode with or without a buffer layer on Si. The crystallinity and surface morphology of the deposited films have been studied using X-ray diffraction and scanning electron microscopy. Electrical properties of the BST films have been evaluated on multilayer oxide electrode using Si/MgAl 2 O 4 /LCMO/BST/Al metal-insulator-metal structure. The bottom electrode interface has shown a marked effect on the electrical properties of the BST films. Current–voltage behavior has indicated the Poole–Frenkel conduction mechanism at higher voltages.

VLSI architecture for low latency radix-4 CORDIC

The CORDIC algorithm, originally proposed using nonredundant radix-2 arithmetic, has been refined in terms of throughput and latency with the introduction of redundant arithmetic and higher radix techniques. In this paper, we propose a pipelined architecture using signed digit arithmetic for the VLSI efficient implementation of rotational radix-4 CORDIC algorithm, eliminating z path completely. A detailed comparison of the proposed architecture with the available radix-2 architectures shows the latency and hardware improvement. The proposed architecture achieves latency improvement over the previously proposed radix-4 architecture with a relatively small hardware overhead. The proposed architecture for 16-bit precision was implemented using VHDL and extensive simulations have been performed to validate the results. The functionally simulated net list has been synthesized for 16-bit precision with 90nm CMOS technology library and the area-time measures are provided. This architecture was also implemented using Xilinx ISE9.1 software and a Virtex device.

Architectural design and FPGA implementation of radix-4 CORDIC processor

A new scaled radix-4 CORDIC architecture that incorporates pipelining and parallelism is presented. The latency of the architecture is n/2 clock cycles and throughput rate is one valid result per n/2 clocks for n bit precision. A 16 bit radix-4 CORDIC architecture is implemented on the available FPGA platform. The corresponding latency of the architecture is eight clock cycles and throughput rate is one valid result per eight clock cycles. The entire scaled architecture operates at 56.96MHz of clock rate with a power consumption of 380mW. The speed can be enhanced with the upgraded version of FPGA device. A speed-area optimized processor is obtained through this architecture and is suitable for real time applications.