Kailash Gopalakrishnan

Phase change memory technology

The authors survey the current state of phase change memory (PCM), a nonvolatile solid-state memory technology built around the large electrical contrast between the highly resistive amorphous and highly conductive crystalline states in so-called phase change materials. PCM technology has made rapid progress in a short time, having passed older technologies in terms of both sophisticated demonstrations of scaling to small device dimensions, as well as integrated large-array demonstrators with impressive retention, endurance, performance, and yield characteristics. They introduce the physics behind PCM technology, assess how its characteristics match up with various potential applications across the memory-storage hierarchy, and discuss its strengths including scalability and rapid switching speed. Challenges for the technology are addressed, including the design of PCM cells for low reset current, the need to control device-to-device variability, and undesirable changes in the phase change material that c...

Overview of candidate device technologies for storage-class memory

Storage-class memory (SCM) combines the benefits of a solid-state memory, such as high performance and robustness, with the archival capabilities and low cost of conventional hard-disk magnetic storage. Such a device would require a solid-state nonvolatile memory technology that could be manufactured at an extremely high effective areal density using some combination of sublithographic patterning techniques, multiple bits per cell, and multiple layers of devices. We review the candidate solid-state nonvolatile memory technologies that potentially could be used to construct such an SCM. We discuss evolutionary extensions of conventional flash memory, such as SONOS (silicon-oxide-nitride-oxide-silicon) and nanotraps, as well as a number of revolutionary new memory technologies. We review the capabilities of ferroelectric, magnetic, phase-change, and resistive random-access memories, including perovskites and solid electrolytes, and finally organic and polymeric memory. The potential for practical scaling to ultrahigh effective areal density for each of these candidate technologies is then compared.

Specifications of Nanoscale Devices and Circuits for Neuromorphic Computational Systems

The goal of neuromorphic engineering is to build electronic systems that mimic the ability of the brain to perform fuzzy, fault-tolerant, and stochastic computation, without sacrificing either its space or power efficiency. In this paper, we determine the operating characteristics of novel nanoscale devices that could be used to fabricate such systems. We also compare the performance metrics of a million neuron learning system based on these nanoscale devices with an equivalent implementation that is entirely based on end-of-scaling digital CMOS technology and determine the technology targets to be satisfied by these new devices. We show that neuromorphic systems based on new nanoscale devices can potentially improve density and power consumption by at least a factor of 10, as compared with conventional CMOS implementations.

Nanoscale electronic synapses using phase change devices

The memory capacity, computational power, communication bandwidth, energy consumption, and physical size of the brain all tend to scale with the number of synapses, which outnumber neurons by a factor of 10,000. Although progress in cortical simulations using modern digital computers has been rapid, the essential disparity between the classical von Neumann computer architecture and the computational fabric of the nervous system makes large-scale simulations expensive, power hungry, and time consuming. Over the last three decades, CMOS-based neuromorphic implementations of “electronic cortex” have emerged as an energy efficient alternative for modeling neuronal behavior. However, the key ingredient for electronic implementation of any self-learning system—programmable, plastic Hebbian synapses scalable to biological densities—has remained elusive. We demonstrate the viability of implementing such electronic synapses using nanoscale phase change devices. We introduce novel programming schemes for modulation of device conductance to closely mimic the phenomenon of Spike Timing Dependent Plasticity (STDP) observed biologically, and verify through simulations that such plastic phase change devices should support simple correlative learning in networks of spiking neurons. Our devices, when arranged in a crossbar array architecture, could enable the development of synaptronic systems that approach the density (∼1011 synapses per sq cm) and energy efficiency (consuming ∼1pJ per synaptic programming event) of the human brain.

Highly-scalable novel access device based on Mixed Ionic Electronic conduction (MIEC) materials for high density phase change memory (PCM) arrays

Phase change memory (PCM) could potentially achieve high density with large, 3Dstacked crosspoint arrays, but not without a BEOL-friendly access device (AD) that can provide high current densities and large ON/OFF ratios. We demonstrate a novel AD based on Cu-ion motion in novel Cu-containing Mixed Ionic Electronic Conduction (MIEC) materials[1, 2]. Experimental results on various device structures show that these ADs provide the ultra-high current densities needed for PCM, exhibit high ON/OFF ratios with excellent uniformity, are highly scalable, and are compatible with <400°C Back-End-Of-the-Line (BEOL) fabrication.

Sub-30nm scaling and high-speed operation of fully-confined Access-Devices for 3D crosspoint memory based on mixed-ionic-electronic-conduction (MIEC) materials

BEOL-friendly Access Devices (AD) based on Cu-containing MIEC materials [1-3] are shown to scale to the <;30nm CDs and <;12nm thicknesses found in advanced technology nodes. Switching speeds at the high (>100uA) currents of NVM writes can reach 15ns; NVM reads at typical (~5uA) current levels can be ≪1usec.

Large-scale (512kbit) integration of multilayer-ready access-devices based on mixed-ionic-electronic-conduction (MIEC) at 100% yield

BEOL-friendly Access Devices (AD) based on Cu-containing MIEC materials [1-4] are integrated in large (512 × 1024) arrays at 100% yield, and are successfully co-integrated together with Phase Change Memory (PCM). Numerous desirable attributes are demonstrated: the large currents (>;200μA) needed for PCM, the bipolar operation required for high-performance RRAM, the single-target sputter deposition essential for high-volume manufacturing, and the ultra-low leakage ( 10 pA) and high voltage margin (1.5V) needed to enable large crosspoint arrays.

Voltage polarity effects in Ge2Sb2Te5-based phase change memory devices

We assess voltage polarity effects in phase-change memory (PCM) devices that contain Ge2Sb2Te5 (GST) as the active material through the study of vertically asymmetric pore-cell and laterally symmetric bridge-cell structures. We show that bias polarity can greatly accelerate device failure in such GST-based PCM devices and, through extensive transmission electron microscopy-based failure analysis, trace these effects to a two-stage elemental segregation process. Segregation is initially driven by bias across the molten region of the cell and is then greatly enhanced during the crystallization process at lower temperatures. These results have implications for the design of pulses and PCM cells for maximum endurance, the use of reverse polarity for extending endurance, the requirements for uni- or bi-polar access devices, the need for materials science on active rather than initial stoichiometries, and the need to evaluate new PCM materials under both bias polarities.

Voltage polarity effects in GST-based phase change memory: Physical origins and implications

We show that bias polarity can greatly accelerate device failure in GST- based (GeSbTe) PCM devices, and trace this effect to elemental segregation, initially driven by bias across the melt but then enhanced during the crystallization process. Implications include device, pulse, and materials design for high endurance.

MIEC (mixed-ionic-electronic-conduction)-based access devices for non-volatile crossbar memory arrays

Several attractive applications call for the organization of memristive devices (or other resistive non-volatile memory (NVM)) into large, densely-packed crossbar arrays. While resistive-NVM devices frequently possess some degree of inherent nonlinearity (typically 3?30? contrast), the operation of large ( 1000?1000 device) arrays at low power tends to require quite large ( 1e7) ON-to-OFF ratios (between the currents passed at high and at low voltages). One path to such large nonlinearities is the inclusion of a distinct access device (AD) together with each of the state-bearing resistive-NVM elements. While such an AD need not store data, its list of requirements is almost as challenging as the specifications demanded of the memory device. Several candidate ADs have been proposed, but obtaining high performance without requiring single-crystal silicon and/or the high processing temperatures of the front-end-of-the-line?which would eliminate any opportunity for 3D stacking?has been difficult.We review our work at IBM Research?Almaden on high-performance ADs based on Cu-containing mixed-ionic-electronic conduction (MIEC) materials [1?7]. These devices require only the low processing temperatures of the back-end-of-the-line, making them highly suitable for implementing multi-layer cross-bar arrays. MIEC-based ADs offer large ON/OFF ratios (), a significant voltage margin (over which current nA), and ultra-low leakage ( 10 pA), while also offering the high current densities needed for phase-change memory and the fully bipolar operation needed for high-performance RRAM. Scalability to critical lateral dimensions 30 nm and thicknesses 15 nm, tight distributions and 100% yield in large (512 kBit) arrays, long-term stability of the ultra-low leakage states, and sub-50 ns turn-ON times have all been demonstrated. Numerical modeling of these MIEC-based ADs shows that their operation depends on mediated hole conduction. Circuit simulations reveal that while scaled MIEC devices are suitable for large crossbar arrays of resistive-NVM devices with low ( 1.2 V) switching voltages, stacking two MIEC devices can support large crossbar arrays for switching voltages up to 2.5 V.