Kailiang Chen

Ultrasonic Imaging Transceiver Design for CMUT: A Three-Level 30-Vpp Pulse-Shaping Pulser With Improved Efficiency and a Noise-Optimized Receiver

This paper demonstrates a four-channel transceiver chip for medical ultrasonic imaging, interfacing to the capacitive micromachined ultrasonic transducers (CMUTs). The high-voltage transmitter (Tx) uses a three-level pulse-shaping technique with charge recycling to improve the power efficiency. The design requires minimum off-chip components and is scalable for more channels. The receiver is implemented with a transimpedance amplifier (TIA) topology and is optimized for tradeoffs between noise, bandwidth, and power dissipation. The test chip is characterized with both acoustic and electrical measurements. Comparing the three-level pulser against traditional two-level pulsers, the measured Tx efficiency shows 56%, 50%, and 43% more acoustic power delivery with the same total power dissipation at 2.5, 3.3, and 5.0 MHz, respectively. The CMUT receiver achieves the lowest noise efficiency factor compared with that of the literature (2.1 compared to a previously reported lowest of 3.6, in units of mPA ·√(mW/Hz). In addition, the transceiver chip is tested as a complete system for medical ultrasound imaging applications, in experiments including Tx beamformation, pulse-echo channel response characterization, and ultrasonic Doppler flow rate detection.

A Column-Row-Parallel ASIC architecture for 3D wearable / portable medical ultrasonic imaging

A Column-Row-Parallel ASIC architecture is proposed to enable 3D wearable / portable medical ultrasound. It offers linear-scaling interconnection, acquisition and programming time, while supporting rich functionality. High voltage MUX in Tx and specially sized source follower in Rx are used to implement parallelization for improved SNR. Fault-tolerant transceiver handles defective transducer elements to increase assembly yield and allow successful system demonstration.

Reconfigurable asynchronous logic automata: (RALA)

Computer science has served to insulate programs and programmers from knowledge of the underlying mechanisms used to manipulate information, however this fiction is increasingly hard to maintain as computing devices decrease in size and systems increase in complexity. Manifestations of these limits appearing in computers include scaling issues in interconnect, dissipation, and coding. Reconfigurable Asynchronous Logic Automata (RALA) is an alternative formulation of computation that seeks to align logical and physical descriptions by exposing rather than hiding this underlying reality. Instead of physical units being represented in computer programs only as abstract symbols, RALA is based on a lattice of cells that asynchronously pass state tokens corresponding to physical resources. We introduce the design of RALA, review its relationships to its many progenitors, and discuss its benefits, implementation, programming, and extensions

Ultrasonic imaging front-end design for CMUT: A 3-level 30Vpp pulse-shaping pulser with improved efficiency and a noise-optimized receiver

A four-channel analog front-end (AFE) transceiver chip for medical ultrasound imaging is demonstrated. The high voltage transmitter uses a 3-level pulse-shaping technique to deliver over 50% more acoustic power for the same power dissipation, compared to traditional methods. The design requires minimum off-chip components and is scalable for more channels. The receiver is implemented with a transimpedance amplifier (TIA) topology and is optimized for noise, bandwidth and power dissipation. Based on both acoustic and electrical measurements, we demonstrate the Transmitter (Tx) efficiency improvement, Tx beamformation and the pulse-echo response, revealing the systems full functionality.

Analog Logic Automata

Analog logic circuits work on digital problems using an analog representation of the digital variables, relaxing the state space of the digital system from the vertices of a hypercube to the interior. This lets us gain speed, power, and accuracy over digital implementations. Logic automata are distributed, scalable and programmable digital computation media with local connections and logic operations. Here we propose analog logic automata (ALA), which relax binary constraints on logic automata states and introduce programmability into analog logic circuits. The localized interaction and scalability of the ALA provide a new way to do neuromorphic engineering, enabling systematic designs in a digital work flow. Low-power, biomedical, decoding and communication applications are described and a 3times3 ALA chip is prototyped, which works at 50 kHz, with a power consumption of 64 muW. With the chip configured as a programmable noise-locked loop (NLL), we obtain a bit error rate (BER) of 1E-7 at an SNR of -1.13 dB.

A column-row-parallel ultrasound imaging architecture for 3d plane-wave imaging and Tx 2nd-order harmonic distortion (HD2) reduction

We propose a Column-Row-Parallel (CRP) architecture for integrated and low-power 3D medical ultrasound imaging applications. CRP offers linear-scaling interconnection, acquisition and programming time, while supporting rich functionality and fault-tolerance against possible transducer element defects. A 16×16 CMUT-ASIC CRP imaging system is fabricated and assembled to demonstrate the highly versatile architecture. 3D plane-wave coherent compounding on CRP facilitates fast frame rate (62.5 volume/s), high quality 3D ultrasonic imaging. An interleaved checker board pattern with I&Q excitations is also demonstrated on CRP for tissue harmonic imaging, reducing CMUT 2nd harmonic distortion (HD2) emission by over 20dB.

A Column-Row-Parallel ASIC Architecture for 3-D Portable Medical Ultrasonic Imaging

This paper presents a scalable column-row-parallel ASIC architecture for 3-D portable medical ultrasound. Through its programmable row-by-row or column-by-column operations for both transmit and receive beam-formation, linear scaling in interconnection, data acquisition complexity, power dissipation, and programming time is achieved. In addition, its per-element controllers can activate fine granularity aperture definition when more functionality is favored over the linear-scaling power and speed efficiency. This front-end architecture is backward compatible to implement existing widely used array aperture patterns, while supporting new imaging apertures and algorithms. It lends itself very well for the combination with integrated or external digital beamforming circuits. A 16 × 16 proof-of-concept ASIC is fabricated and flip-chip bonded to a 16 × 16 capacitive micromachined ultrasonic transducer (CMUT). Each three-level pulsing transmitter (Tx) is 46% more power efficient than a traditional two-level version, with high-voltage (HV) multiplexers (MUXs) designed for flexible Tx parallelization. Each low-noise receiver (Rx) consumes 1.4 mW active power and 54 μW sleep power, with optimized source follower stages to combine analog outputs for improved SNR. The transceivers are also fault-tolerant to inevitable defects in transducers, greatly enhancing assembly yield. The system demonstrates 3-D plane-wave generation to implement the coherent compounding algorithm for fast volume rate (62.5 volume/s), high-quality 3-D ultrasonic imaging. An interleaved checker board pattern with Iand Q excitations is also demonstrated for ultrasonic harmonic imaging, which reduces transmitted second harmonic distortion (HD2) by over 20 dB.

System energy model for a digital ultrasound beamformer with image quality control

As the lateral resolution and axial imaging depth of a ultrasound image increase, so do the number of transducer elements and the corresponding processing units. Conventional ultrasound systems are often large and expensive due to the intensive requirement of large beamforming arrays. But for applications such as point-of-care diagnostics in rural areas, the movement to a portable and low-power ultrasound imaging system is warranted. To address the low power requirement for portable applications, the proposed beamformer operates in one of three modes, namely quarter, half, and full resolution modes, selectable at runtime. In the first two modes, a subset of elements, with effective pitches of 4x and 2x of the transducer pitch, are processed for low quality images of the full region of interest. These modes provide run-time power reduction, because the Analog Front End (AFE) and Analog-to-Digital Converter (ADC) for the unused channels can be turned off by the feedback control signals from the beamformer. Based on the low quality image, the user can intuitively specify a smaller region where a higher quality image is desired, and the full resolution beamforming mode is used. A system energy model is set up to evaluate the image quality and frame rate performance, while providing realistic power consumption predictions. The model offers fast and accurate behavioral level understanding of the ultrasound system under optimization.

Cryptography with asynchronous logic automata

We introduce the use of asynchronous logic automata (ALA) for cryptography. ALA aligns the descriptions of hardware and software for portability, programmability, and scalability. An implementation of the A5/1 stream cipher is provided as a design example in a concise hardware description language, Snap, and we discuss a power- and timing-balanced cell design.