Hae-Seung Lee

Full-speed testing of A/D converters

Improved computer-aided analog-to-digital converter (ADC) characterization methods based on the code density test and spectral analysis using the fast Fourier transform are described. The code density test produces a histogram of the digital output codes of an ADC sampling a known input. The code density can be interpreted to compute the differential and integral nonlinearities, gain error, offset error, and internal noise. Conversion-rate and frequency-dependent behavior can also be measured.

A 15-b 1-Msample/s digitally self-calibrated pipeline ADC

A 15-b 1-Msample/s digitally self-calibrated pipeline analog-to-digital converter (ADC) is presented. A radix 1.93, 1 b per stage design is employed. The digital self-calibration accounts for capacitor mismatch, comparator offset, charge injection, finite op-amp gain, and capacitor nonlinearity contributing to DNL. A THD of -90 dB was measured with a 9.8756-kHz sine-wave input. The DNL was measured to be within +or-0.25 LSB at 15 b, and the INL was measured to be within +or-1.25 LSB at 15 b. The die area is 9.3 mm*8.3 mm and operates on +or-4-V power supply with 1.8-W power dissipation. The ADC is fabricated in an 11-V, 4-GHz, 2.4- mu m BiCMOS process. >

A self-calibrating 15 bit CMOS A/D converter

A self-calibrating analog-to-digital converter using binary weighted capacitors and resistor strings is described. Linearity errors are corrected by a simple digital algorithm. A folded cascode CMOS comparator resolves 30 /spl mu/V in 3 /spl mu/s. An experimental converter fabricated using a 6-/spl mu/m-gate CMOS process demonstrates 15-bit resolution and linearity at a 12-kHz sampling rate.

Comparator-based switched-capacitor circuits for scaled CMOS technologies

A comparator-based switched-capacitor circuit (CBSC) technique is presented for the design of analog and mixed-signal circuits in scaled CMOS technologies. The technique involves replacing the operational amplifier in a standard switched-capacitor circuit with a comparator and a current source. During charge transfer, the comparator detects the virtual ground condition in place of the opamp which normally forces the virtual ground condition. A prototype 1.5-bit/stage 10-bit 7.9-MS/s pipeline ADC was designed using the comparator-based switched-capacitor technique. The prototype ADC was implemented in 0.18-mum CMOS. It achieves an ENOB of 8.6 bits for a 3.8-MHz input signal and dissipates 2.5 mW

Comparator-Based Switched-Capacitor Circuits for Scaled CMOS Technologies

A comparator-based switched-capacitor (CBSC) design method for sampled-data systems utilizes topologies similar to traditional opamp-based methods but relies on the detection of the virtual ground using a comparator instead of forcing it with feedback. A prototype 10b CBSC 1.5b/stage pipelined ADC is implemented in a 0.18mum CMOS process. The converter operates at 8MHz and consumes 2.5mW

A 2.5 V 12 b 5 MSample/s pipelined CMOS ADC

This 1.2 /spl mu/m, 33 mW analog-to-digital converter (ADC) demonstrates a family of power reduction techniques including a commutated feedback capacitor switching (CFCS), sharing of the second stage of an op amp between adjacent stages of a pipeline, reusing the first stage of an op amp as the comparator pre-amp, and exploiting parasitic capacitance as common-mode feedback capacitors.

A low-power reconfigurable analog-to-digital converter

A reconfigurable analog-to-digital converter digitizes signals over a 1 Hz-10 MHz bandwidth and 6 to 16 b resolution with adaptive power consumption. The converter achieves this by reconfiguring between pipeline and /spl Delta//spl Sigma/ architectures and adjusting circuit parameters and bias currents.

A high-swing CMOS telescopic operational amplifier

A high-swing, high-performance CMOS telescopic operational amplifier is described. The high swing of the op-amp is achieved by employing the tail and current source transistors in the deep linear region. The resulting degradation in differential gain, common-mode rejection ratio (CMRR), and other amplifier characteristics are compensated by applying regulated-cascode differential gain enhancement and a replica-tail feedback technique. A prototype of the op-amp has been built in a 0.81-/spl mu/m CMOS process. Operating from a power supply of 3.3 V, it achieves a differential swing of /spl plusmn/2.15 V, a differential gain of 90 dB, unity-gain frequency of 90 MHz, and >50-dB CMRR. It is shown, analytically and through simulations, that the operational amplifier maintains its high CMRR even at high frequencies.

A 12-b 600 ks/s digitally self-calibrated pipelined algorithmic ADC

This paper discusses fully digital error correction and self-calibration which correct errors due to capacitor mismatch, charge injection, and comparator offsets in algorithmic A/D converters. The calibration is performed without any additional analog circuitry, and the conversion does not need extra clock cycles. This technique can be applied to algorithmic converter configurations including pipelined, cyclic, or pipelined cyclic configurations. To demonstrate the concept, an experimental 2-stage pipelined cyclic A/D converter is implemented in a standard 1.6-/spl mu/m CMOS process. The ADC operates at 600 ks/s using 45 mW of power at /spl plusmn/2.5 V supplies. The active die area excluding the external logic circuit is 1 mm/sup 2/. Maximum DNL of /spl plusmn/0.6 LSB and INL of /spl plusmn/1 LSB at a 12-b resolution have been achieved. >

A 200-MHz CMOS phase-locked loop with dual phase detectors

The authors describe a 200-MHz PLL (phase-locked loop) in a 2- mu m CMOS technology employing an untrimmed current-controlled ring oscillator (CCO). Two phase detectors are included: a phase-frequency detector (PFD) for fast acquisition during data preamble (100% pulse density), and a mixer phase detector to lock on actual data (in the presence of missing pulses). Simulation results and experimental data using an external current source suggest that using the bandgap reference, the CCO supply sensitivity will be 4%/V and the CCO temperature coefficient will be about 500 p.p.m./ degrees C. Internal input and output waveforms in lock were measured from buffered test pads with a low-capacitance wideband buffered probe.<<ETX>>