Kailiang Lu

Driving Device Comparison for Phase-Change Memory

A study is conducted to investigate the relative advantages of different driving devices for phase-change memory cells using 3-D numerical device simulation. Among various possible choices, p-n diodes and vertical gate-all-around (GAA) metal-oxide-semiconductor field-effect transistors (MOSFETs) are studied in detail as they represent distinct classes of driving devices. Different performance parameters including cell size, current drive, disturb immunity, power dissipation, and scalability are carefully compared. While p-n diodes show superiority in technology nodes with large device dimensions, the scaling process has improved the performance of GAA MOSFETs significantly to outperform that of p-n diodes in extremely scaled technologies.

Comparison of PN diodes and FETs as Phase Change Memory (PCM) driving devices

In this study, the current driving capability of PN diodes and field effect transistors (FETs) for phase change memory (PCM) applications is investigated. To have a fair comparison, vertical gate-all-around (GAA) MOSFETs with similar cross-section as the PN diodes are selected for comparison. Through extensive 3-D device simulations have been performed based on existing experimental data from the 90 nm to 22 nm technology node, PN diodes are found to be a better choice for delivering higher programming currents down to 22 nm technology node due to the higher effective cross-sectional area of current flow. In addition, the GAA MOSFETs are subject to serious cross-talk issues that may limit their performance in PCM applications.

Optimized Scaling of Diode Array Design for 32nm Node Phase Change Memory

In this work, a compact physical model with diode access devices for PCM technology is developed and verified with extensive 2-D and 3-D device simulations. The choice of design parameters allows the operation of the diode access device to serve as a bipolar junction transistor (BJT) for the same physical structure. The PCM array design with these devices is optimized for the 90 nm, 45 nm and 32 nm technology nodes based on this compact model and further verified by 3-D numerical device simulation.