Kalle Tammemäe

Reconfigurable Multiplier for Virtex FPGA Family

This paper describes integer multiplier design optimizations for FPGA technology. The changes in partial product generator component enable to infer CLB fast carry logic for building Wallace trees. This change increases speed and gives better resource allocation.

Automatic FSM Synthesis for Low-power Mixed Synchronous/Asynchronous Implementation

Power consumption in a synchronous FSM (Finite-State Machine) can be reduced by partitioning it into a number of coupled sub-FSMs where only the part that is involved in a state transition is clocked. Automatic synthesis of a partitioned FSM includes a partitioning algorithm and sub-FSM synthesis to an implementation architecture. In this paper, we first introduce an implementation architecture for partitioned FSMs that uses gated-clock technique for disabling idle parts of the circuits and asynchronous controllers for communication between the sub-FSMs. We then describe a new transformation procedure for the sub-FSM. The FSM synthesis flow has been automated in a prototype tool that accepts an FSM specification. The tool generates synthesizable RT-level VHDL code with identical cycle-to-cycle input/output behavior in accordance with the specification. An average power reduction of 45% has been obtained for a set standard FSM benchmarks.

Modular Exponent Realization on FPGAs

The article describes modular exponent calculations used widely in cryptographic key exchange protocols. The measures for hardware consumption and execution speed based on argument bit width and algorithm rank are created. The partitioning of calculations is analyzed with respect to interconnect signal numbers and added delay. The partitioned blocks are used for implementation approximations of two different multiplier architectures. Examples are provided for 3 families of FPGAs: XC4000, XC6200 and FLEX10k

Flexible Codesign Target Architecture for Early Prototyping of CMIST Systems

We present an architecture for rapid prototyping of selected controldominated HW parts resulting from HW/SW cosynthesis. Our codesign toolkit AKKA[1], which targets to design of control intensive s ...

FPL Curriculum at Tallinn Technical University

This paper describes reconfigurable logic in education at Tallinn Technical University (TTU) in the light of rapid changes of countrys economical structure and information technology environment. A logical set of courses has been introduced at every educational direction of Computer Engineering (CE) along with the set of design tools, prototyping boards and reconfigurable platforms.The courses, hardware and design tools, utilized for educating the field programmable logic and mixed hardware/software systems are described.