Kamakoti Veezhinathan

Constructing Online Testable Circuits Using Reversible Logic

With the advent of nanometer technology, circuits are more prone to transient faults that can occur during its operation. Of the different types of transient faults reported in the literature, the single-event upset (SEU) is prominent. Traditional techniques such as triple-modular redundancy (TMR) consume large area and power. Reversible logic has been gaining interest in the recent past due to its less heat dissipation characteristics. This paper proposes the following: 1) a novel universal reversible logic gate (URG) and a set of basic sequential elements that could be used for building reversible sequential circuits, with 25% less garbage than the best reported in the literature; (2) a reversible gate that can mimic the functionality of a lookup table (LUT) that can be used to construct a reversible field-programmable gate array (FPGA); and (3) automatic conversion of any given reversible circuit into an online testable circuit that can detect online any single-bit errors, including soft errors in the logic blocks, using theoretically proved minimum garbage, which is significantly lesser than the best reported in the literature.

LFSR based stream ciphers are vulnerable to power attacks

Linear Feedback Shift Registers (LFSRs) are used as building blocks for many stream ciphers, wherein, an n-degree primitive connection polynomial is used as a feedback function to realize an n-bit LFSR. This paper shows that such LFSRs are susceptible to power analysis based Side Channel Attacks (SCA). The major contribution of this paper is the observation that the state of an n-bit LFSR can be determined by making O(n) power measurements. Interestingly, neither the primitive polynomial nor the value of n be known to the adversary launching the proposed attack. The paper also proposes a simple countermeasure for the SCA that uses n additional flipflops.

Network-on-Chips on 3-D ICs: Past, Present, and Future

Abstract Interconnects have become the chief bottleneck in today’s era of chip design. Along the road of interconnect evolution, Network-on-Chips (NoCs) have emerged as a structured and scalable solution for connecting computational elements on a very large scale integration chip. Also, with the deep-submicron technology allowing integration of billions of transistors, chips have grown very complex and large in size. The global wire-length problem was addressed with the integration of devices in the third dimension (3-D). The combination of 3-D integration and a scalable interconnect, like NoCs, promise to revolutionize design for Chip Multi-processors, System-on-chips, and System-in-package. This paper surveys on all the advancements in 3-D NoCs.

A low-bit rate segment vocoder using minimum residual energy criteria

In speech coding, segment vocoders offer good intelligibility at low bit rates. A segment vocoder has four basic components 1)Segmentation of input speech 2)Segment quantization 3)Residual quantization 4)Synthesis of speech. Most segment vocoders use a recognition approach to segment quantization. In this paper, we assume a different approach to segment quantization. The segmental unit is a syllable and the segment codebook stores the sequence of LPC vectors. During the encoding process the speech segment is quantized using the sequence of LPC vectors that result in the smallest residual energy. PESQ scores indicate that this vocoder achieves better quality compared to that of a corresponding vocoder that uses a speech recognition framework.

A Method for Integrating Network-on-Chip Topologies with 3D ICs

Three dimensional integration is a promising approach for reducing the form factor of chips. Scalable Networks on Chips (NoCs) are a necessity to support the communication requirements of such 3D ICs. Mapping of NoC topologies onto the different layers of the 3D stack, while meeting the 3D technology requirements and application power-performance constraints is an important problem. In this paper, we present an algorithm that addresses this issue of performing 3D layer assignment of NoC components. We also integrate the algorithm with an existing NoC interconnect floor planner. Our experiments on many SoC benchmarks show a reduction of 8 - 10% in the NoC power consumption and a 49% reduction in the number of vertical links (and hence, the Through Silicon Vias (TSVs)) when compared to existing approaches.

A Programmable Event-driven Architecture for Evaluating Spiking Neural Networks

Spiking neural networks (SNNs) represent the third generation of neural networks and are expected to enable new classes of machine learning applications. However, evaluating large-scale SNNs (e.g., of the scale of the visual cortex) on power-constrained systems requires significant improvements in computing efficiency. A unique attribute of SNNs is their event-driven nature—information is encoded as a series of spikes, and work is dynamically generated as spikes propagate through the network. Therefore, parallel implementations of SNNs on multi-cores and GPGPUs are severely limited by communication and synchronization overheads. Recent years have seen great interest in deep learning accelerators for non-spiking neural networks, however, these architectures are not well suited to the dynamic, irregular parallelism in SNNs. Prior efforts on specialized SNN hardware utilize spatial architectures, wherein each neuron is allocated a dedicated processing element, and large networks are realized by connecting multiple chips into a system. While suitable for large-scale systems, this approach is not a good match to size or cost constrained mobile devices. We propose PEASE, a Programmable Event-driven processor Architecture for SNN Evaluation. PEASE comprises of Spike Processing Units (SPUs) that are dynamically scheduled to execute computations triggered by a spike. Instructions to the SPUs are dynamically generated by Spike Schedulers (SSs) that utilize event queues to track unprocessed spikes and identify neurons that need to be evaluated. The memory hierarchy in PEASE is fully software managed, and the processing elements are interconnected using a two-tiered bus-ring topology matching the communication characteristics of SNNs. We propose a method to map any given SNN to PEASE such that the workload is balanced across SPUs and SPU clusters, while pipelining across layers of the network to improve performance. We implemented PEASE at the RTL level and synthesized it to IBM 45 technology. Across 6 SNN benchmarks, our 64-SPU configuration of PEASE achieves 7.1×−17.5× and 2.6×−5.8× speedups, respectively, over software implementations on an Intel Xeon E5-2680 CPU and NVIDIA Tesla K40C GPU. The energy reductions over the CPU and GPU are 71×−179× and 198×−467×, respectively.

Shakti-T: A RISC-V Processor with Light Weight Security Extensions

With increased usage of compute cores for sensitive applications, including e-commerce, there is a need to provide additional hardware support for securing information from memory based attacks. This work presents a unified hardware framework for handling spatial and temporal memory attacks. The paper integrates the proposed hardware framework with a RISC-V based micro-architecture with an enhanced application binary interface that enables software layers to use these features to protect sensitive data. We demonstrate the effectiveness of the proposed scheme through practical case studies in addition to taking the design through a VLSI CAD design flow. The proposed processor reduces the metadata storage overhead up to 4 x in comparison with the existing solutions, while incurring an area overhead of just 1914 LUTs and 2197 flip flops on an FPGA, without affecting the critical path delay of the processor.

Component fault localization using switching current measurements

Conventional manufacturing/system tests point to a set of logically equivalent faults and not the exact fault within a faulty component. In this paper, we show that during testing, measuring the current drawn by a faulty component aids in identifying the exact manifested fault within it. We propose to partition the chips power grid based on the chips component partitions, and dedicate a external supply pin to each component partition. In order to minimize the cost associated with the external measurement circuitry, we reuse the scan resources available within the flip-flop to repeatedly apply the desired test-pattern pair, so that the average current measured during the launch-to-capture window, is equal to the same over a long period of time. The proposed technique is validated by simulating the power-grid and the modified flip-flop using SPICE circuit simulator. The proposed technique, when applied to several component benchmark circuits, helped to localize almost all the logically equivalent faults.

Using timers to switch-off TCAM banks in routers

Ternary Content Addressable Memory (TCAM) is the de-facto standard for route lookup in routers. While TCAMs support fast packet header lookup, they also consume high power. In this paper, we propose algorithms to save power in routers by dynamically switching-on/off TCAM banks based on their usage. Using three timers that monitor the usage of TCAMs, we remove unused entries and save TCAM space. As a result, unused TCAM banks in distributed linecards of routers can be switched-off. The algorithm used to switch-on the TCAM banks ensures that no packets are lost during header lookup, but introduces extra lookup delay. We show that by introducing parallel search for header lookup, the additional delay can be avoided. Simulations, conducted in software, serve to highlight that it is indeed possible to achieve power savings by using the proposed algorithms. The proposed methods are mainly applicable for campus and enterprise networks, where compaction of prefixes can be readily achieved.