Seetal Potluri

LPScan: An algorithm for supply scaling and switching activity minimization during test

Existing low power testing techniques either focus on reducing the switching activity neglecting supply voltage, or perform supply voltage scaling without attempting to minimize switching activity. In this paper we propose LPScan (Low Power Scan), which integrates supply scaling and switching activity reduction in a single framework to reduce test power. For a shift frequency of 125MHz, the LPScan algorithm when applied to circuits from the ISCAS, OpenCores and ITC benchmark suite, produced power savings of 80% in the best case and 50% in the average case, compared to the best known algorithm [1].

BioChipWork: Reverse Engineering of Microfluidic Biochips

Microfluidic biochip is an emerging platform that has wide applications in areas of immunoassays, DNA sequencing and point-of-care health service. This paper presents BioChipWork, the first practical framework for automatic reverse engineering and IP piracy of microfluidic biochips. Our work targets two types of presently available microfluidic biochips which are characterized based on working mechanisms: flow-based microfluidic biochip (FMFB) and droplet-based microlfuidic biochip (DMFB). More specifically, BioChipWork identifies two practical sets of reverse engineering attacks and demonstrates the attacks using our developed algorithm and an open source synthesis tool. In the first attack, the attacker extracts the hardware layout of the pertinent FMFB based on image analysis. In the second attack, the attacker reconstructs the proprietary protocol mapped onto the DMFB by analyzing the actuation sequence or the video frames recorded by the CCD camera. The proposed reverse engineering attacks are non-intrusive, scalable and easy to implement, rendering the IP of authentic owners in danger. As countermeasures to obscure the functional layout and reduce information leakage from side-channels, we suggest novel biochip camouflaging and obfuscation techniques.

PinPoint: An algorithm for enhancing diagnostic resolution using capture cycle power information

Conventional ATPG tools help in detecting only the equivalence class to which a fault belongs and not the fault itself. This paper presents PinPoint, a technique that further divides the equivalence class into smaller sets based on the capture power consumed by the circuit under test in the presence of different faults in it, thus aiding in narrowing down on the fault. Applying the technique on ITC benchmark circuits yielded significant improvement in diagnostic resolution.

Thermal-Safe Dynamic Test Scheduling Method Using On-Chip Temperature Sensors for 3D MPSoCs

System test and online test techniques are aggressively being used in today’s SoCs for improved test quality and reliability (e.g., aging/soft-error robustness). With gaining popularity of vertical integration such as 2.5D and 3D, in the semiconductor industry, ensuring thermal safety of SoCs during these test modes poses a challenge. In this paper, we propose a dynamic test scheduling mechanism for system tests and/or online test that uses dynamic feedback from on-chip thermal sensors to control temperature during shift (or scan) and capture, thereby ensuring thermal-safe conditions while applying the test patterns. The proposed technique is a closed loop test application scheme that eliminates the need for separate thermal simulation of test patterns at design stage. The technique also enables granular field-level configuration of thermal limits, so that different units across multiple cores are subjected to customized thermal profiles. Results from implementation of the proposed schemes on a 4-layer, 16-core, 12.8 million gates, OpenSparc S1 processor subsystem are presented.

Synthesis of on-chip control circuits for mVLSI biochips

Microfluidic VLSI (mVLSI) biochips help perform biochemistry at miniaturized scales, thus enabling cost, performance and other benefits. Although biochips are expected to replace biochemical labs, including point-of-care devices, the off-chip pressure actuators and pumps are bulky, thereby limiting them to laboratory environments. To address this issue, researchers have proposed methods to reduce the number of offchip pressure sources, through integration of on-chip pneumatic control logic circuits fabricated using three-layer monolithic membrane valve technology. Traditionally, mVLSI biochip physical design was performed assuming that all of the control logic is off-chip. However, the problem of mVLSI biochip physical design changes significantly, with introduction of on-chip control, since along with physical synthesis, we also need to (i) perform on/off-chip control partitioning, (ii) on-chip control circuit design and (iii) the integration of on-chip control in the placement and routing design tasks. In this paper we present a design methodology for logic synthesis and physical synthesis of mVLSI biochips that use on-chip control. We show how the proposed methodology can be successfully applied to generate biochip layouts with integrated on-chip pneumatic control.

Optimal Don’t Care Filling for Minimizing Peak Toggles During At-Speed Stuck-At Testing

Due to the increase in manufacturing/environmental uncertainties in the nanometer regime, testing digital chips under different operating conditions becomes mandatory. Traditionally, stuck-at tests were applied at slow speed to detect structural defects and transition fault tests were applied at-speed to detect delay defects. Recently, it was shown that certain cell-internal defects can only be detected using at-speed stuck-at testing. Stuck-at test patterns are power hungry, thereby causing excessive voltage droop on the power grid, delaying the test response, and finally leading to false delay failures on the tester. This motivates the need for peak power minimization during at-speed stuck-at testing. In this article, we use input toggle minimization as a means to minimize a circuit’s power dissipation during at-speed stuck-at testing under the Combinational State Preservation scan (CSP-scan) Design-For-Testability (DFT) scheme. For circuits whose test sets are dominated by don’t cares, this article maps the problem of optimal X-filling for peak input toggle minimization to a variant of the interval coloring problem and proposes a Dynamic Programming (DP) algorithm (DP-fill) for the same along with a theoretical proof for its optimality. For circuits whose test sets are not dominated by don’t cares, we propose a max scatter Hamiltonian path algorithm, which ensures that the ordering is done such that the don’t cares are evenly distributed in the final ordering of test cubes, thereby leading to better input toggle savings than DP-fill. The proposed algorithms, when experimented on ITC99 benchmarks, produced peak power savings of up to 48% over the best-known algorithms in literature. We have also pruned the solutions thus obtained using Greedy and Simulated Annealing strategies with iterative 1-bit neighborhood to validate our idea of optimal input toggle minimization as an effective technique for minimizing peak power dissipation during at-speed stuck-at testing.

Component fault localization using switching current measurements

Conventional manufacturing/system tests point to a set of logically equivalent faults and not the exact fault within a faulty component. In this paper, we show that during testing, measuring the current drawn by a faulty component aids in identifying the exact manifested fault within it. We propose to partition the chips power grid based on the chips component partitions, and dedicate a external supply pin to each component partition. In order to minimize the cost associated with the external measurement circuitry, we reuse the scan resources available within the flip-flop to repeatedly apply the desired test-pattern pair, so that the average current measured during the launch-to-capture window, is equal to the same over a long period of time. The proposed technique is validated by simulating the power-grid and the modified flip-flop using SPICE circuit simulator. The proposed technique, when applied to several component benchmark circuits, helped to localize almost all the logically equivalent faults.

Post-Synthesis Circuit Techniques for Runtime Leakage Reduction

We consider the problem of reducing active mode leakage power by modifying the post-synthesis net lists of combinational logic blocks. The stacking effect is used to reduce leakage power, but instead of a separate signal one of the inputs to the gate itself is used. The approach is studied on multiplier blocks. It is found that a significant number of nets have high probabilities of being constant at 0 or 1. In specific applications such as those having high peak to average ratio, like audio and other signal processing applications, this effect is more pronounced. We show how these signals can be used to put gates to sleep, thus saving significant leakage power.