Kamal El-Sankary

High-Speed AES Encryptor With Efficient Merging Techniques

This letter presents a new efficient architecture for high-speed advanced encryption standard (AES) encryptor. This technique is implemented using composite field arithmetic byte substitution, where higher efficiency is achieved by merging and location rearrangement of different operations required in the steps of encryption. The proposed architecture is presented with multistage subpipelined architecture that allows having higher efficiency in terms of (throughput/area) than any previous field-programmable gate array (FPGA) implementations.

Noise-Cancelling CMOS Active Inductor and Its Application in RF Band-Pass Filter Design

A CMOS active inductor with thermal noise cancelling is proposed. The noise of the transistor in the feed-forward stage of the proposed architecture is cancelled by using a feedback stage with a degeneration resistor to reduce the noise contribution to the input. Simulation results using 90 nm CMOS process show that noise reduction by 80% has been achieved. The maximum resonant frequency and the quality factor obtained are 3.8 GHz and 405, respectively. An RF band-pass filter has been designed based on the proposed noise cancelling active inductor. Tuned at 3.46 GHz, the filter features total power consumption of 1.4 mW, low noise figure of 5 dB, and IIP3 of −10.29 dBm.

A digital blind background capacitor mismatch calibration technique for pipelined ADC

A new digital background calibration technique to compensate for the capacitor mismatch in pipelined analog-to-digital converter (ADC) is presented. A digital signal from the ADC output is constructed so as to transform the capacitor mismatch to gain error. A simple modification to the conventional multiplying digital-to-analog converter (MDAC) allows the ADC to toggle between different configurations to create a reference signal used to calibrate blindly the ADC in the background. The creation of this signal does not produce any limitation for the ADC in terms of speed or degrading the input dynamic range. Simulation results show the effectiveness of this new method.

New sampling method to improve the SFDR of time-interleaved ADCs

Modern communication systems need high-speed ADCs with wide spurious-free dynamic range (SFDR). Conventional time-interleaved ADCs suffer from spurious components that seriously affect the SFDR. Improvement in the SFDR has been achieved by randomizing the samples of the analog input between the different ADC channels at the expense of adding more ADCs and more analog circuitry to the architecture, which increases the complexity of the system as a whole. In this paper, we present the mathematical background describing the effect of randomizing the samples among the interleaved ADCs and we propose a digitally oriented method, based on this analysis, to randomize the mismatches among the ADC channels. Analysis and behavioral simulations show the effectiveness of the proposed approach in multi-channel ADCs with arbitrary bit resolution and sampling rate. For a 10 bit 500 MS/sec ADC, the SFDR achieved using the proposed randomizing method can be as wide as -79 dBc, which is an enhancement of more than 30 dB compared to the conventional time interleaved ADC.

Enhanced RF to DC CMOS rectifier with capacitor-bootstrapped transistor

This paper presents a high efficient multi-stages full-wave RF to DC rectifier for RFID applications. The proposed converter employs diode-connected transistors with gate to drain bootstrapping capacitor to overcome threshold drop of voltage. Rectifying transistors are biased in triode region to improve the driving capability of the circuit while they operate at lower input voltages. Bulk biasing technique is applied to ensure faster turn on for level shifting transistors. Simulation results in 90nm CMOS technology at frequency of 920MHz, show that output voltage and power conversion efficiency at low input power level are improved compare to conventional rectifier using diode-connected transistors.

A background calibration technique for multibit/stage pipelined and time-interleaved ADCs

A digital background calibration technique to compensate for the nonlinearity and gain error in the sub-digital-to-analog converter (SDAC), and the operational amplifier finite dc gain in multibit/stage pipelined analog-to-digital converter (ADC) is proposed. By injecting subtractive calibration voltages in a modified conventional multibit multiplying DAC and performing correlation based successive coefficient measurements, a background calibration is performed. This calibration technique does not need an accurate reference voltage or an increasing in the SDAC resolution. A global gain correction essential for time-interleaved ADCs is presented. Simulation results show that in the presence of realistic capacitor and resistance mismatch and finite op-amp gain, this technique improves the linearity by several bits in single and multi-channel pipelined ADC

Low power, low voltage, 10bit-50MSPS pipeline ADC dedicated for front-end ultrasonic receivers

This paper concerns the design and the implementation of a low power, low voltage 10bit-50MS/s pipeline analog to digital converter (ADC) dedicated to ultrasonic receivers. The ADC is used in the front-end stage to convert the signals coming from the time gain compensator (TGC) of the handheld ultrasonic apparatus. The proposed architecture is based on 1.5 bits per stage pipeline structure followed by a digital offset compensation to relax the constraints on the analog circuitry. The converter is implemented in digital CMOS 0.18 /spl mu/m technology, the circuit occupies an active area of 1.2 mm/sup 2/, the input differential voltage dynamic range is chosen to be 1.6 Vpp and the power consumption is found to be 31 mW from 1.8 V supply.

Bandgap reference with curvature corrected compensation using subthreshold MOSFETs

A bandgap reference with curvature corrected compensation which utilizes the subtraction of currents generated from complementary NMOS and PMOS bandgaps using MOS transistors in subthreshold is presented. A transimpedance amplifier with accurate input current compensation is used to overcome the problems due to input common range limitations of operational amplifiers. The bandgap reference uses power supply of 0.8V, the accuracy is 19ppm/K for 386mV in the temperature range of 0 to 130C. The PSRR is 24dB for 1kHz and 23dB for 10kHz.

Distortion Analysis Using Volterra Series and Linearization Technique of Nano-Scale Bulk-Driven CMOS RF Amplifier

The distortion analysis of nano-scale bulk-driven (BD) CMOS RF amplifier is presented based on Volterra series. The first three-order Volterra kernels are computed; and the closed-form expressions of the second-order and third-order harmonic distortion (HD) are derived. These expressions give good accuracy comparing with the simulation results, and can provide insight into the nonlinearity of nano-scale BD amplifier. These expressions unveil and demonstrate that the nano-scale BD MOSFET has distinct nonlinear characteristics. Also, distortion-aware design guidelines for nano-meter CMOS BD amplifier are provided. A modified second-order intermodulation (IM2) injection technique is presented to suppress the third-order intermodulation (IM3) product. This modified technique which consumes only 64 μA current employs phase adjustment of the low-frequency IM2; and up to 20 dB IM3 reduction is achieved over 1 MHz-20 MHz two-tone spacing range without gain reduction or noise penalty.

Design of low-voltage wide tuning range CMOS multipass voltage-controlled ring oscillator

This paper presents an 0.8-V power supply multi-pass loop ring oscillator. The oscillator employs cross-coupled PMOS transistors to improve phase noise characteristic and multi-pass loop to obtain wide frequency tuning range. The coarse and fine controlled signals are also applied to lower the noise sensitivity of the oscillator. Simulations using TSMC 90 nm CMOS technology shows 394MHz to 4.4GHz frequency tuning range and −94.6dBc/Hz at 1MHz offset from 4.4GHz. The power consumption is 11.2mW.