Kamel Beznia

A Tool for Analog/RF BIST Evaluation Using Statistical Models of Circuit Parameters

Testing analog integrated circuits is expensive in terms of both test equipment and time. To reduce the cost, Design-For-Test techniques (DFT) such as Built-In Self-Test (BIST) have been developed. For a given Circuit Under Test (CUT), the choice of a suitable technique should be made at the design stage as a result of the analysis of test metrics such as test escapes and yield loss. However, it is very hard to carry out this estimation for analog/RF circuits by using fault simulation techniques. Instead, the estimation of parametric test metrics is made possible by Monte Carlo circuit-level simulations and the construction of statistical models. These models represent the output parameter space of the CUT in which the test metrics are defined. In addition, models of the input parameter space may be required to accelerate the simulations and obtain higher confidence in the DFT choices. In this work, we describe a methodological flow for the selection of most adequate statistical models and several techniques that can be used for obtaining these models. Some of these techniques have been integrated into a Computer-Aided Test (CAT) tool for the automation of the process of test metrics estimation. This estimation is illustrated for the case of a BIST solution for CMOS imager pixels that requires the use of advanced statistical modeling techniques.

Accurate analog/RF BIST evaluation based on SVM classification of the process parameters

The analog/RF functional test which is based on specification circuit testing is very costly due to lengthy test times and highly sophisticated test equipment. Alternative test measures, extracted by means of Built-in Self Test (BIST) techniques, are a promising approach to replace standard specification-based tests. However, these test measures must be evaluated at the design stage by estimating the Test Escapes (Te) and the Yield Loss (Yl). An accurate estimation of these metrics requires a large non-biased sample of circuit instances including parametric defective ones. A necessary number of these circuits cannot be obtained with a Monte Carlo simulation alone. Statistical learning techniques, in combination with Monte Carlo simulation, can allow the generation of such a sample for multivariate test metrics estimation. The development of Extreme Value Theory (EVT) has provided a rigorous tool for the computation of parametric test metrics. However, this theory is very complex and difficult to apply in the case of multivariate problems. In this paper, we propose an improvement of this approach. The classification of the circuits is based on the specifications and the test limits instead of the extreme thresholds and no post-classification simulation is necessary. Also, we illustrate the use of this model for the evaluation of a filter BIST technique.

Accurate estimation of analog test metrics with extreme circuits

Specification-based testing of analog/RF circuits is very costly due to lengthy test times and highly sophisticated test equipment. Alternative test measures, extracted by means of Built-In Test (BIT) techniques, are a promising approach to replace standard specification-based tests. However, these test measures must be evaluated at the design stage, before the real production, by estimating parametric test errors such as Test Escapes (TE) and Yield Loss (YL). An accurate estimation of these metrics requires a large non-biased sample of circuit instances including parametric defective ones. Since these extreme circuits are rare events, they cannot be obtained with a Monte Carlo simulation of an affordable size. However, statistical learning techniques, in combination with Monte Carlo simulation, can allow the generation of such a sample for multivariate test metrics estimation. In this paper, we will demonstrate this technique for the evaluation of an RF LNA BIT technique for which a large database of 106 circuits has been simulated for comparison purposes.

Statistical modelling of analog circuits for test metrics computation

Analog Built-In Test (BIT) techniques should be evaluated at the design stage, before the real production, by estimating the analog test metrics, namely Test Escapes (TE) and Yield Loss (YL). Due to the lack of comprehensive fault models, these test metrics are estimated under process variations. In this paper, we estimate the joint cumulative distribution function (CDF) of the output parameters of a Circuit Under Test (CUT) from an initial small sample of devices obtained from Monte Carlo circuit simulation. We next compute the test metrics in ppm (parts-per-million) directly from this model, without sampling the density as in previous works. The test metrics are obtained very fast since the computation does not depend on the size of the output parameter space and there is no need for density sampling. An RF LNA modeled with a Gaussian copula is used to compare the results with past approaches.

Parametric Test Metrics Estimation Using Non-gaussian Copulas

The evaluation of parametric test metrics for analog/RF test techniques requires an accurate multivariate statistical model of output parameters of the device under test, namely performances and test measurements. In this paper, we will use Copulas theory for deriving such a model. A copulas-based model separates the dependencies between these output parameters from their marginal distributions, providing a complete and scale-free description of dependence that is more suitable to be modeled using well known multivariate parametric laws. Previous works have used Gaussian copulas for modeling the dependencies between the output parameters for some types of devices (e.g RF LNA). This paper will illustrate the use of Archimedean copulas for modeling non-Gaussian dependencies. In particular, a Clayton copula will be used to model the dependencies between the output parameters of a case-study test technique for CMOS imagers. Parametric test metrics such as pixel false acceptance and false rejection will be estimated using the derived model.

Analog performance prediction based on archimedean copulas generation algorithm

Testing analog circuits is a complex and very time consuming task. In contrary to digital circuits, testing analog circuits needs different configurations, each of them targets a certain set of output parameters which are the performances and the test measures. One of the solutions to simplify the test task and optimize test time is the reduction of the number of to-be-tested performances by eliminating redundant ones. However, the main problem with such a solution is the identification of redundant performances. Traditional methods based on calculation of the correlation between different performances or on the defect level are shown to be not sufficient. This paper presents a new method based on the Archimedean copula generation algorithm. It predicts the performance value from each output parameter value based on the dependence (copula) between the two values. Therefore, different performances can be represented by a single output parameter; as a result, less test configurations are required. To validate the proposed approach, a CMOS imager with two performances and one test measure is used. The simulation results show that the two performances can be replaced by a single test measure. Industrial results are also reported to prove the superiority of the proposed approach.1