Salvador Mir

Defect Filter for Alternate RF Test

Alternate RF testing is a very promising candidate for replacing the costly standard specification-based approach. The defect filter in the alternate test flow is a crucial preparatory step for the overall success of alternate test. In this paper, we present a novel nonlinear defect filter based on an estimate of the joint probability density function of the alternate measurements. The construction of the filter does not require a defect dictionary and can accommodate any underlying density without needing any prior knowledge regarding its parametric form.

Evaluation of Analog/RF Test Measurements at the Design Stage

We present a method that is capable of handling process variations to evaluate analog/RF test measurements at the design stage. The method can readily be used to estimate test metrics, such as parametric test escape and yield loss, with parts per million accuracy, and to fix test limits that satisfy specific tradeoffs between test metrics of interest. Furthermore, it provides a general framework to compare alternative test solutions that are continuously being proposed toward reducing the high cost of specification-based tests. The key idea of the method is to build a statistical model of the circuit under test and the test measurements using nonparametric density estimation. Thereafter, the statistical model can be simulated very fast to generate an arbitrarily large volume of new data. The method is demonstrated for a previously proposed built-in self-test measurement for low-noise amplifiers. The result indicates that the new synthetic data have the exact same structure of data generated by a computationally intensive brute-force Monte Carlo circuit simulation.

Estimation of Test Metrics for the Optimisation of Analogue Circuit Testing

The estimation of test metrics such as defect level, test yield or yield loss is important in order to quantify the quality and cost of a test approach. For design-for-test purposes, this is important in order to select the best test measurements but this must be done at the design stage, before production test data is made available. In the analogue domain, previous works have considered the estimation of these metrics for the case of single faults, either catastrophic or parametric. The consideration of single parametric faults is sensitive for a production test technique if the design is robust. However, in the case that production test limits are tight, test escapes resulting from multiple parametric deviations may become important. In addition, aging mechanisms result in field failures that are often caused by multiple parametric deviations. In this paper, we will consider the estimation of analogue test metrics under the presence of multiple parametric deviations (or process deviations) and under the presence of faults. A statistical model of a circuit is used for setting test limits under process deviations as a trade-off between test metrics calculated at the design stage. This model is obtained from a Monte Carlo circuit simulation, assuming Gaussian probability density functions (PDFs) for the parameter and performance deviations. After setting the test limits considering process deviations, the test metrics are calculated under the presence of catastrophic and parametric single faults for different potential test measurements. We will illustrate the technique for the case of a fully differential operational amplifier, proving the validity in the case of this circuit of the Gaussian PDF.

Fault-based ATPG for linear analog circuits with minimal size multifrequency test sets

An automatic test pattern generation (ATPG) procedure for linear analog circuits is presented in this work. A fault-based multifrequency test approach is considered. The procedure selects a minimal set of test measures and generates the minimal set of frequency tests which guarantee maximum fault coverage and, if required, maximal fault diagnosis, of circuit AC hard/soft faults. The procedure is most suitable for linear time-invariant circuits which present significant frequency-dependent fault effects.For test generation, the approach is applicable once parametric tests have determined DC behaviour. The advantage of this procedure with respect to previous works is that it guarantees a minimal size test set. For fault diagnosis, a fault dictionary containing a signature of the effects of each fault in the frequency domain is used. Fault location and fault identification can be achieved without the need of analog test points, and just in-circuit checkers with an observable go/no-go digital output are required for diagnosis.The procedure is exemplified for the case of an analog biquadratic filter. Three different self-test approaches for this circuit are considered. For each self-test strategy, a set of several test measures is possible. The procedure selects, in each case, the minimal set of test measures and the minimal set of frequency tests which guarantee maximum fault coverage and maximal diagnosis. With this, the self-test approaches are compared in terms of the fault coverage and the fault diagnosability achieved.

Electrically induced stimuli for MEMS self-test

A major problem for applying self-test techniques to MEMS is the multi-domain nature of the sensing parts that require special test equipment for stimuli generation. In this work we describe, for three different types of MEMS that work in different energy domains, how the required nonelectrical test stimuli can be induced onchip by means of electrical signals. This provides the basis for adding BIST strategies for MEMS parts embedded in the coming generation of integrated systems. The first case corresponds to an accelerometer as a review of a classical example. The last two cases correspond to piezoresistive and infrared sensors that we use in innovative applications under development in our Laboratory, and for which the self-test methods are new to our knowledge. The last case is also illustrated as a complete application that corresponds to an infrared imager. The on-chip test signal generation proposed requires only slight modifications and allows production test of the imager with a standard test equipment, without the need of special infrared sources and the associated optical equipment. The test function can also be activated off-line in the field for validation and maintenance purposes.

Diagnosis of Local Spot Defects in Analog Circuits

We present a method for diagnosing local spot defects in analog circuits. The method aims to identify a subset of defects that are likely to have occurred and suggests to give them priority in a classical failure analysis. For this purpose, the method relies on a combination of multiclass classifiers that are trained using data from fault simulation. The method is demonstrated on an industrial large-scale case study. The device under consideration is a controller area network transceiver used in automobile systems. This device demands high-quality control due to the reliability requirements of the application wherein it is deployed. The diagnosis problem is discussed by taking into consideration the realities of this case study.

Generation of Electrically Induced Stimuli for MEMS Self-Test

A major task for the implementation of Built-In-Self-Test (BIST) strategies for MEMS is the generation of the test stimuli. These devices can work in different energy domains and are thus designed to sense signals which are generally not electrical. In this work, we describe, for different types of MEMS, how the required non-electrical test stimuli can be induced on-chip by means of electrical signals. This provides the basis for adding BIST strategies for MEMS parts embedded in the coming generation of integrated systems. The on-chip test signal generation is illustrated for the case of MEMS transducers which exploit such physical principles as time-varying electrostatic capacitance, piezo-resistivity effect and Seebeck effect. These principles are used in devices such as accelerometers, infrared imagers, pressure sensors or tactile sensors. For implementation, we have used two major MEMS technologies including CMOS-compatible bulk micromachining and surface micromachining. We illustrate the ability to generate on-chip test stimuli and to implement a self-test strategy for the case of a complete application. This corresponds to an infrared imager that can be used in multiple applications such as overheating detection, night vision, and earth tracking for satellite positioning. The imager consists of an array of thermal pixels that sense an infrared radiation. Each pixel is implemented as a suspended membrane that contains several thermopiles along the different support arms. The on-chip test signal generation proposed requires only slight modifications and allows a production test of the imager with a standard test equipment, without the need of special infrared sources and the associated optical equipment. The test function can also be activated off-line in the field for validation and maintenance purposes.

Design of self-checking fully differential circuits and boards

A design methodology for on-line testing analog linear fully differential (FD) circuits is presented in this work. The test strategy is based on concurrently monitoring via an analog checker the common mode (Chi) at the inputs of all amplifiers, The totally self-checking (TSC) goal is achieved for linear FD implementations provided that the checker CM threshold is small enough with respect to the specified margins of erroneous behavior in the circuit outputs. The design methodology is illustrated for a switched-capacitor biquadratic filter and the self-checking properties evaluated for a hard/soft-fault model. A large checker threshold of 100 mV of CM is chosen since the filter implementation does not minimize nonidealities (e.g., amplifier offsets or clock feedthrough) which result in significant CM components. The circuit outputs are accepted to deviate within a 10% band. With the implemented checker, the TSC goal is not achieved for some faults in narrow regions of the frequency band. For the worst case, a hard fault which results in a 31% deviation is undetected in only a narrow band of approximately 310 Hz. The circuit can be made TSC with a checker threshold of 40 mV and an accepted output deviation of 15%. This is, however, more demanding on the checker (which currently takes less than 3% of the total area and about 7.6% of the total power) and requires an improved filter implementation to reduce CM components. Our solution consists of relaxing a bit the TSC property of the functional block and applying a periodical off-line test to make the checker strongly code disjoint (SCD). This is easy to implement since an off-line test is also required for the checker. The checker outputs a double-rail error indication which ensures compatibility with digital checkers and makes the design of self-checking mixed signal circuits straightforward. The circuit-level mixed-signal approach is extended to the board level by means of the IEEE Std. 1149.1 digital test bus.

Extending fault-based testing to microelectromechanical systems

As stable fabrication processes for MicroElectroMechanical Systems (MEMS) emerge, research efforts shift towards the design of systems of increasing complexity. The ways in which testing is going to be performed for large volume complex devices embedding MEMS are not known. As in the microelectronics industry, the development of cost-effective tests for larger systems may well require test stimuli targeting actual faults, developing fault lists and fault models for realistic manufacturing defects and failure modes, and using fault simulation as a major approach for assessing testability and dependability. In this paper, we illustrate how fault-based testing can be extended to MEMS, both for bulk and surface micromachining technologies, making possible the reuse of analog testing techniques.

Sensors for built-in alternate RF test

The paper discusses a variety of sensors to enable a built-in test in RF devices. The list of sensors includes dummy circuits, process control monitors, DC probes, an envelope detector, and a current sensor. Dummy circuits and process control monitors are simple circuits that do not tap into the signal path of the RF device. Instead, they monitor the device by virtue of being subject to the same process variations. Their outputs form an alternative measurement pattern which can be mapped to the performances of the device using a typical alternate test flow. The rest of the sensors are physically connected to the RF device, thus they can detect random catastrophic defects within it and, as an auxiliary benefit, they can improve the accuracy in predicting its performances. The degradation that these sensors incur is carefully assessed and the RF device is co-designed with them to correct for the losses. The operation and test efficiency of the sensors is demonstrated for the case of an RF LNA using post-layout simulations.