Kamran Farzan

A CMOS 10-gb/s power-efficient 4-PAM transmitter

A novel power-efficient architecture for a multilevel pulse amplitude modulation (PAM) transmitter is proposed. A data-look-ahead technique is used to pre-switch the current sources so that drive current is reduced when transmitting small voltage levels. This technique also eliminates the need for a pre-driver block, which also saves transmitter power. Based on this architecture, a 4-PAM transmitter is designed in 0.18-/spl mu/m standard digital CMOS technology. The transmitter achieves 3.5 GS/s (7 Gb/s) with a 1.7-V supply and 5 GS/s (10 Gb/s) with a 2-V supply and it occupies an area of 0.16 mm/sup 2/. The output driver and the entire transmitter consume only 11.25 and 66 mW at 7 Gb/s (20 and 121 mW at 10 Gb/s), respectively, which are the lowest reported powers at this speed.

Coding schemes for chip-to-chip interconnect applications

Increasing demand for high-speed interchip interconnects requires faster links that consume less power. The Shannon limit for the capacity of these links is at least an order of magnitude higher than the data rate of the current state-of-the-art designs. Channel coding can be used to approach the theoretical Shannon limit. Although there are numerous capacity-approaching codes in the literature, the complexity of these codes prohibits their use in high-speed interchip applications. This work studies several suitable coding schemes for chip-to-chip communication and backplane application. These coding schemes achieve 3-dB coding gain in the case of an additive white Gaussian noise (AWGN) model for the channel. In addition, a more realistic model for the channel is developed here that takes into account the effect of crosstalk, jitter, reflection, inter-symbol interference (ISI), and AWGN. Interestingly, the proposed signaling schemes are significantly less sensitive to such interference. Simulation results show coding gains of 5-8 dB for these methods with three typical channel models. In addition, low-complexity decoding architectures for implementation of these schemes are presented. Finally, circuit simulation results confirm that the high-speed implementations of these methods are feasible.

Differential signaling with a reduced number of signal paths

Differential signaling is often used for digital chip-to-chip interconnects because it provides common-mode noise rejection. Unfortunately, differential signals generally require 2N signal paths to communicate N signals. In this paper, a method for differential signaling is described that requires as few as N+1 signal paths for N signals. Using this method, the signal values appear incrementally between neighboring matched signal paths. The technique, called incremental signaling, is similar to dicode (1-D) partial response signaling except that the sequence is transmitted in parallel over a bus of wires rather than sequentially in time. Theoretical and simulated bit error rates are presented for several possible implementations of an encoder/transmitter and receiver/decoder for a digital data bus including peak detection and maximum likelihood sequence detection (MLSD). Peak detection uses N+1 signal paths and results in a 3-dB performance degradation with respect to independent noise compared with fully differential signaling. The Viterbi algorithm for MLSD uses N+2 signal paths but provides only a 1.25 dB improvement over peak detection due to correlated noise on the (1-D)-coded sequence. Modified Viterbi algorithms that use N+2 signal paths are introduced to cancel the correlated noise sources, resulting in a bit error rate performance comparable with fully differential signaling.

A power-efficient architecture for high-speed D/A converters

A novel power-efficient architecture for high-speed D/A converters is proposed. A data look ahead technique is used to pre-switch the current sources so that the DAC current is reduced when generating small voltage levels. Interestingly, this technique also eliminates the need for a pre-driver block for each current-cell, which also saves power. Based on this architecture, a 6-bit DAC is designed in 0.18/spl mu/m standard digital CMOS technology. The update rate for this DAC is 1GS/s and it consumes only 24mW at 1GS/s.

A Robust 4-PAM Signaling Scheme for Inter-Chip Links Using Coding in Space

Increasing demand for high-speed inter-chip interconnects requires faster links that consume less power. Channel coding can be used to lower the required signal-to-noise ratio for a specific bit error rate in a channel. There are numerous codes that can be used to approach the theoretical Shannon limit, which is the maximum information transfer rate of a communication channel for a particular noise level. However, the complexity of these codes prohibits their use in high-speed inter-chip applications. A low-complexity signaling scheme is proposed here. This method can achieve 3-5-dB coding gain over uncoded four-level pulse amplitude modulation (PAM). The receiver for this signaling scheme along with a regular 4-PAM receiver was designed and implemented in a 0.18-mum standard CMOS technology. Experimental results show that the receiver is functional up to 2.5 Gb/s. This was verified with a bit error rate tester (BERT) and we were able to achieve error free operation at 2.5-Gb/s channel transfer rate. The entire receiver for this scheme consumes 22 mW at 2.5 Gb/s and occupies an area of 0.2 mm 2.

A power-efficient 4-PAM signaling scheme with convolutional encoder in space for chip-to-chip communication

Increasing demand for high-speed inter-chip interconnects requires faster links that consume less power. The Shannon limit for the capacity of these links is at least an order of magnitude higher than the data rate of the current state-of-the-art designs. Channel coding can be used to approach the theoretical Shannon limit. Although there are numerous capacity-approaching codes in the literature, the complexity of these codes prohibits their use in high-speed inter-chip applications. A low-complexity signaling scheme is proposed which can achieve 3-5 dB coding gain over uncoded 4-level pulse amplitude modulation (PAM). The receiver for this signaling scheme, along with a regular 4-PAM receiver, was designed and implemented in a 0.18 /spl mu/m standard digital CMOS technology. Experimental results show that the receiver is functional up to 2.5 Gb/s. The entire receiver for this scheme consumes only 22 mW at 2.5 Gb/s and occupies an area of 0.2 mm/sup 2/.

A low-complexity power-efficient signaling scheme for chip-to-chip communication

Multi-level signaling can be used to reduce the number of required signal paths. However, it needs more power to combat its impact on bit error rate (BER). It has been shown that coding theory can be used to alleviate this problem. The complexity of these coding schemes is a major concern for high-speed implementation. This paper describes a novel low-complexity method for an analog implementation of a previously proposed coding scheme. This new architecture not only reduces the complexity of the receiver but also improves its performance. Moreover, a more realistic model for the channel, which takes into account the effect of reflection and inter-symbol interference (ISI), is developed. Simulation results show that this scheme provides roughly 5 dB gain over the ordinary 4-PAM scheme for two practical channels in chip-to-chip communication.

A low-power crosstalk-insensitive signaling scheme for chip-to-chip communication

Increasing demand for high-speed inter-chip interconnects requires faster links that consume less power. The Shannon limit for the capacity of these links is at least an order of magnitude higher than the data rate of the current state-of-the-art designs. A novel signaling scheme is proposed that can provide 3 dB coding gain. This signaling scheme is significantly less sensitive to crosstalk, inter-symbol interference and residual reflection compared to the ordinary binary signaling scheme. Moreover, a low-complexity architecture for high-speed implementation of this method is proposed. Finally, an extension of this scheme is presented, which shows better performance at the expense of adding more complexity.