Kang-Yeob Park

10-Gb/s 850-nm CMOS OEIC Receiver With a Silicon Avalanche Photodetector

We present a 10-Gb/s optoelectronic integrated circuit (OEIC) receiver fabricated with standard 0.13-μm complementary metal-oxide-semiconductor (CMOS) technology for 850-nm optical interconnect applications. The OEIC receiver consists of a CMOS-compatible avalanche photodetector (CMOS-APD), a transimpedance amplifier (TIA), an offset cancellation network, a variable equalizer (EQ), a limiting amplifier (LA), and an output buffer. The CMOS-APD provides high responsivity as well as large photodetection bandwidth. The TIA is composed of two-stage differential amplifiers with high feedback resistance of 4 kΩ. The EQ compensates high-frequency loss by controlling the boosting gain with a capacitor array. The LA consists of five-stage gain cells with active feedback and negative capacitance to achieve broadband performance. With the OEIC receiver, we successfully demonstrate transmission of 10-Gb/s optical data at 850 nm with a bit error rate of 10-12 at the incident optical power of -4 dBm. The OEIC receiver has the core chip area of about 0.26 mm2 and consumes about 66.8 mW.

High-Speed CMOS Integrated Optical Receiver With an Avalanche Photodetector

We present a high-speed monolithically integrated optical receiver fabricated with 0.13-mum standard complementary metal-oxide-semiconductor (CMOS) technology. The optical receiver consists of a CMOS-compatible avalanche photodetector (CMOS-APD) and a transimpedance amplifier (TIA). The CMOS-APD provides high responsivity as well as large bandwidth. Its bandwidth is further enhanced by the TIA having negative capacitance, which compensates undesired parasitic capacitance. With the CMOS integrated optical receiver, 4.25-Gb/s optical data are successfully transmitted with a bit-error rate less than 10-12 at the incident optical power of - 5.5 dBm.

An integrated 12.5-Gb/s optoelectronic receiver with a silicon avalanche photodetector in standard SiGe BiCMOS technology.

An optoelectronic integrated circuit (OEIC) receiver is realized with standard 0.25-μm SiGe BiCMOS technology for 850-nm optical interconnect applications. The OEIC receiver consists of a Si avalanche photodetector, a transimpedance amplifier with a DC-balanced buffer, a tunable equalizer, and a limiting amplifier. The fabricated OEIC receiver successfully detects 12.5-Gb/s 2(31)-1 pseudorandom bit sequence optical data with the bit-error rate less than 10(-12) at incident optical power of -7 dBm. The OEIC core has 1000 μm x 280 μm chip area, and consumes 59 mW from 2.5-V supply. To the best of our knowledge, this OEIC receiver achieves the highest data rate with the smallest sensitivity as well as the best power efficiency among integrated OEIC receivers fabricated with standard Si technology.

Design of 250-Mb/s Low-Power Fiber Optic Transmitter and Receiver ICs for POF Applications

This paper describes 250-Mb/s fiber optic transmitter and receiver ICs for plastic optical fiber applications using a 0.18-μm CMOS technology. Simple signal and light detection schemes are introduced for power reduction in sleep mode. The transmitter converts non-return-to-zero digital data into 650-nm visible-red light signal and the receiver recovers the digital data from the incident light signal through up to 50-m plastic optical fiber. The transmitter and receiver ICs occupy only 0.62 mm 2 of area including electrostatic discharge protection diodes and bonding pads. The transmitter IC consumes 23 mA with 20 mA of LED driving currents, and the receiver IC consumes 16 mA with 4 mA of output driving currents at 250 Mb/s of data rate from a 3.3-V supply in active mode. In sleep mode, the transmitter and receiver ICs consume only 25 μA and 40 μA, respectively.

SNR characteristics of 850-nm OEIC receiver with a silicon avalanche photodetector

We investigate signal-to-noise ratio (SNR) characteristics of an 850-nm optoelectronic integrated circuit (OEIC) receiver fabricated with standard 0.25-µm SiGe bipolar complementary metal-oxide-semiconductor (BiCMOS) technology. The OEIC receiver is composed of a Si avalanche photodetector (APD) and BiCMOS analog circuits including a transimpedance amplifier with DC-balanced buffer, a tunable equalizer, a limiting amplifier, and an output buffer with 50-Ω loads. We measure APD SNR characteristics dependence on the reverse bias voltage as well as BiCMOS circuit noise characteristics. From these, we determine the SNR characteristics of the entire OEIC receiver, and finally, the results are verified with bit-error rate measurement.

A fully-integrated 12.5-Gb/s 850-nm CMOS optical receiver based on a spatially-modulated avalanche photodetector

We present a fully integrated 12.5-Gb/s optical receiver fabricated with standard 0.13-µm complementary metal-oxide-semiconductor (CMOS) technology for 850-nm optical interconnect applications. Our integrated optical receiver includes a newly proposed CMOS-compatible spatially-modulated avalanche photodetector, which provides larger photodetection bandwidth than previously reported CMOS-compatible photodetectors. The receiver also has high-speed CMOS circuits including transimpedance amplifier, DC-balanced buffer, equalizer, and limiting amplifier. With the fabricated optical receiver, detection of 12.5-Gb/s optical data is successfully achieved at 5.8 pJ/bit. Our receiver achieves the highest data rate ever reported for 850-nm integrated CMOS optical receivers.

A 4-channel 12.5Gb/s Common-Gate Transimpedance Amplifier Array for DVI/HDMI Applications

In this paper, a four-channel 12.5-Gb/s differential transimpedance amplifier (TIA) array is realized in a 0.18-mum standard CMOS technology for the applications of digital visual interface (DVI) and high-definition multimedia interface (HDMI) cables. By exploiting the common-gate configuration as input stage, the TIA relaxes the design tradeoffs between the bandwidth and the large photodiode capacitance. Post-layout simulations demonstrate that a single channel TIA achieves 64-dBH transimpedance gain, 3.125-Gb/s operations with 2.1-GHz bandwidth for 2-pF input parasitic capacitance including photodiode capacitance and ESD protection pad capacitance, and 1.52-muA average input noise current that corresponds to -18dBm sensitivity for 10-12 BER. The 4-channel TIA array consumes 200-mW from a single 1.8-V supply.

A bandwidth adjustable integrated optical receiver with an on-chip silicon avalanche photodetector

A bandwidth adjustable integrated optical receiver having an on-chip silicon avalanche photodetector is realized with standard 0.25-μm silicon-germanium bipolar complementary metal-oxidesemiconductor technology for optical interconnect applications. With the controllable capacitive degeneration technique, the optical receiver bandwidth can be adjusted for the best bit error rate performance.

A 2.5Gb/s ESD-protected dual-channel optical transceiver array

This paper describes the design of a dual-channel optical transceiver array realized in a standard 0.18 mum CMOS technology for the applications of high-speed digital interface. The transmitter drives a 2-channel VCSEL array at 2.5 Gb/s, equipped with the APC (5-15 mA) and AMC (4-20 mApp) loops for constant and reliable optical power outputs. Meanwhile, the receiver exploits the common-gate transimpedance amplifier, demonstrating 87 dBOmega transimpedance gain, 1.4 GHz bandwidth for 2 pF input parasitic capacitance, -18 dBm sensitivity for 10-12 BER, and less than -20 dB crosstalk between TX and RX within the bandwidth. The whole 2-channel transceiver array chip dissipates 500 mW.

Low-power 850 nm optoelectronic integrated circuit receiver fabricated in 65 nm complementary metal–oxide semiconductor technology

The authors present a low-power 850 nm Si optoelectronic integrated circuit (OEIC) receiver fabricated in standard 65 nm complementary metal–oxide semiconductor (CMOS) technology. They analyse power consumption of previously reported CMOS OEIC receivers and determine the authors receiver architecture for low-power operation. Their OEIC receiver consists of a CMOS-compatible avalanche photodetector and electronic circuits that include an inverter-based transimpedance amplifier, a tunable equaliser and a post amplifier. With the fabricated OEIC receiver, they successfully demonstrate 8 Gb/s operation with a bit-error rate <10−12 at incident optical power of −4.5 dBm. Their OEIC receiver consumes 5 mW with 1.2 V supply voltage. To the best of their knowledge, their OEIC receiver achieves the lowest energy efficiency among 850 nm CMOS OEIC receivers.