Wonseok Oh

A CMOS Low-Dropout Regulator With Current-Mode Feedback Buffer Amplifier

Current feedback amplifiers (CFAs) provide fast response and high slew rate with Class-AB operation. Fast response, low-dropout regulators (LDRs) are critical for supply regulation of deep-submicron analog baseband and RF system-on-chip designs. An LDR with an CFA-based second stage driving the regulation field-effect transistor is presented. The low dropout (LDO) achieves an output noise spectral density of 67.7 nV radicHz, and PSR of 38 dB, both at 100 kHz. In comparison to an equivalent power consumption voltage feedback buffer LDO, the proposed CFA-based LDO settles 60% faster, achieving 0.6- settling time for a 25-mA load step. The LDO with CFA buffer is designed and fabricated on a 0.25- CMOS process with five layers of metal, occupying 0.23- silicon area.

A CMOS Low Noise, Chopper Stabilized Low-Dropout Regulator With Current-Mode Feedback Error Amplifier

Low 1/f noise, low-dropout (LDO) regulators are becoming critical for the supply regulation of deep-submicron analog baseband and RF system-on-chip designs. A low-noise, high accuracy LDO regulator (LN-LDO) utilizing a chopper stabilized error amplifier is presented. In order to achieve fast response during load transients, a current-mode feedback amplifier (CFA) is designed as a second stage driving the regulation FET. In order to reduce clock feed-through and 1/f noise accumulation at the chopping frequency, a first-order digital SigmaDelta noise-shaper is used for chopping clock spectral spreading. With up to 1 MHz noise-shaped modulation clock, the LN-LDO achieves a noise spectral density of 32 nV/radic(Hz) and a PSR of 38 dB at 100 kHz. The proposed LDO is shown to reduce the phase noise of an integrated 32 MHz temperature compensated crystal oscillator (TCXO) at 10 kHz offset by 15 dB. Due to reduced 1/f noise requirements, the error amplifier silicon area is reduced by 75%, and the overall regulator area is reduced by 50% with respect to an equivalent noise static regulator. The current-mode feedback second stage buffer reduces regulator settling time by 60% in comparison to an equivalent power consumption voltage mode buffer, achieving 0.6 mus settling time for a 25-mA load step. The LN-LDO is designed and fabricated on a 0.25 mum CMOS process with five layers of metal, occupying 0.88 mm2.

A CMOS Low-Noise, Low-Dropout Regulator for Transceiver SOC Supply Management

Low-noise, low-dropout (LN-LDO) regulators are critical for supply regulation of deep-submicron analog baseband and RF system-on-chip designs. A low 1/f noise LDO regulator utilizing a chopper stabilized error amplifier is introduced. A secondary amplifier with supply ripple subtraction stage is used for PSR improvement. With the proposed techniques, less than 180 nV/radicHz output noise spectral density and 50 dB of PSR is measured at 10 kHz frequency. With chopping frequencies up to 1MHz, the regulator achieves 5 mV/25 mA load regulation at 100 muA quiescent current. The LN-LDO is designed and fabricated on a 0.25mum, digital CMOS process with five level metal occupying 0.54 mm2.

A Low 1/f Noise CMOS Low-Dropout Regulator with Current-Mode Feedback Buffer Amplifier

Low-noise, low-dropout (LN-LDO) regulators are critical for supply regulation of deep-submicron analog baseband and RF system-on-chip designs. A low 1/f noise LDO regulator utilizing a chopper stabilized error amplifier is presented. In order to achieve fast response during load transients, a current-mode feedback amplifier (CFA) with an asymmetrical input pair is designed as a second stage. With chopping frequencies up to 1MHz, an output noise spectral density of 32nV/radicHz and PSR of 38dB is achieved at 100kHz. Compared to an equivalent noise density static regulator, the error amplifier silicon area is reduced by 75%. With the current-mode feedback second stage buffer, settling time is reduced by 60% in comparison to an equivalent power consumption voltage mode buffer, achieving 0.6musec settling time for a 50mA load step. The LN-LDO is designed and fabricated on a 0.25 mum CMOS process with five layers of metal, occupying 0.88mm2

CMOS fast-settling time low pass filter associated with voltage reference and current limiter for low dropout regulator

In this work, a fast turn-on settling low dropout regulator (LDO) with current limiter is presented. Dynamically operating the proposed current limiter using a decent current comparator protects the IC from any damage when an overload condition occurs or the output of the regulator is shorted. A novel low pass filter associated with voltage reference circuit, which provides highly filtered reference voltage and fast settling time, is implemented to minimize output noise due to voltage reference noise. The LDO with proposed low pass filter and current limiter has been implemented in a 0.6µm n-well CMOS process. The LDO dissipates 65µA quiescent current at 150mA full load condition and its output noise is 407.8nV/√Hz at 100Hz. Turn-on settling time of the LDO is 45µsec and threshold current of the current limiter is set to 230mA of output load current.

A fast transient response shunt low dropout regulator

In this paper, the proposed shunt regulator is presented. Compared with a series voltage regulator, the shunt voltage regulator gives wideband power supply rejection (PSR) and fast transient response at the expense of large quiescent current. In this paper, a novel shunt regulator architecture is proposed to achieve the genuine characteristic of a shunt regulator with small quiescent current. The proposed shunt regulator transient response is 3.98μsec over full load current rising step and it is at least 3.5 times faster than series regulator. PSR characteristic of the proposed shunt regulator shows −22.4 dB up to 200 kHz.