Kaoru Kawamura
Fujitsu
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Publication
Featured researches published by Kaoru Kawamura.
international conference on computer aided design | 1990
Kaoru Kawamura; Tatsuya Shindo; Toshiyuki Shibuya; Hideki Miwatari; Y. Ohki
A novel general routing algorithm is presented. Each net is routed to minimize the cost function defined by a weighted sum of penalties. Two types of design rule violations, touches and crosses, are factors of the cost function. Using these violations enables the algorithm to achieve 100% completion even when routing problems have nets which must be considered simultaneously. This type of problem could not be routed completely by conventional rip-up routers. The algorithm was implemented on a newly developed massively parallel computer. Experimental results on Bursteins difficult switch box problem and several small printed circuit boards show that the algorithm is as powerful as a human expert designer.<<ETX>>
design automation conference | 1986
Kaoru Kawamura; Masanobu Umeda; Hiroshi Shiraishi
In this paper we will discuss a new automatic routing method for printed circuit boards(PCBs). In the field of automatic PCB routing, several “rip-up and reroute” techniques (“dynamic routing”) have recently been proposed. Dynamic routing works by changing one or more previously routed features, and identifying unrouted connections in a new configuration. Dynamic routing is an important idea, because it has the possibility of 100% completion by automating the wire embedding that was formerly done manually. The method we propose here is based on dynamic routing. Its distinctive feature lies in the organization of three levels of hierarchy; grid routing, local dynamic routing, and global dynamic routing. In recent experiments with this method, improvement in both routing completion rate and processing time has been obtained.
symposium on frontiers of massively parallel computation | 1990
Toshiyuki Shibuya; Kaoru Kawamura; Tatsuya Shindo; Hideki Miwatari; Y. Ohki
The massively parallel layout engine, MAPLE, an SIMD computer that provides very high computing power for CAD applications, is discussed. MAPLE uses up to 64K processors, each having a 32-kB memory, a 512-b data register, and an ALU. The system clock rate is 20 MHz. 64K processors in parallel produce an aggregate of 40-billion 32-b integer additions per second. Parallel routing, the architecture, and the software are covered.<<ETX>>
international symposium on quality electronic design | 2003
Toshiyuki Shibuya; Rajeev Murgai; Toshiaki Kondo; Kazuhiro Emi; Kaoru Kawamura
In this paper, we propose a new physical synthesis methodology, PDL, which relaxes the timing constraints to obtain best optimality in terms of layout quality and timing quality. It provides a common database for delay calculation, logic optimization, placement, and routing tools so that they can work and interact closely. We present results on industrial circuits showing the efficacy of this methodology.
field programmable logic and applications | 2015
Yutaka Tamiya; Yoshinori Tomita; Toshiyuki Ichiba; Kaoru Kawamura
In this paper we propose a new breakpoint mechanism, which improves controllability of in-circuit debug. It monitors data packets transmitted on the interface port of the target hardware, and triggers a breakpoint when a specified packet is detected among them in realtime. Regarding a data packet as a series of data sequences, we employ an efficient data sequence matching circuit, which is general purpose and is not restricted to specific protocols or applications. Owing to linearity of CRC (Cyclic Redundancy Check) and co-operation with a software debugger, that matching method is implemented with a simple in-circuit debug module, and achieves at-speed and realtime detection of specified data sequences. Moreover, changing breakpoint conditions does not require hardware re-implementation, but requires just modifying values of data registers inside the debug module. We expect this brings verification operators enormous reduction of both efforts and TAT (Turn-Around-Time) for in-circuit debug. Our experimental results show our proposed method can be implemented in an efficient hardware with small area overheads, and can work with enough accuracy and speed for practical use.
Active and Passive Electronic Components | 1981
Hiroshi Shiraishi; Kaoru Kawamura; Masaaki Hayashi
In hybrid integrated circuit mask design, the design quality largely depends on the designers experience and creativity. It is difficult to completely automate the design process as is done with LSIs or printed circuit boards. It is important to incorporate flexibility into the system.
Archive | 1989
Tatsuya Shido; Kaoru Kawamura; Masanobu Umeda; Toshiyuki Shibuya; Hideki Miwatari
Archive | 1990
Tatsuya Shindo; Kaoru Kawamura
Archive | 1989
Tatsuya Shindo; Kaoru Kawamura; Masanobu Umeda; Toshiyuji C O Fujitsu Shibuya; Hideki Miwatari
Archive | 1987
Kaoru Kawamura; Hideki Mito; Hiroshi Shiraishi; Masanobu Umeda