Yutaka Tamiya

Application of Boolean unification to combinational logic synthesis

The authors present various applications of Boolean unification to combinational logic synthesis. Three topics of combinational logic synthesis are discussed: redesign, multilevel logic minimization, and minimization of Boolean relations. All of these problems can be uniformly formalized as Boolean unification problems. Experimental results are also reported.<<ETX>>

LP based cell selection with constraints of timing, area, and power consumption

This paper presents a new LP based optimal cell selection method. Optimal cell selection is a useful tool for final tuning of LSI designs. It replaces drivabilities of cells, adjusting timing, area, and power constraints. Using the latest and earliest arrival times, it can handle both setup and hold time constraints. We also make an efficient initial basis, which speeds up a simplex LP solver by 5 times without any relaxations nor approximations. From experimental results, it reduces the clock cycle of a manual designed 13k-transistor chip by 17% without any increase of area.

Fast cycle estimation methodology for instruction-level emulator

In this paper, we propose a cycle estimation methodology for fast instruction-level CPU emulators. This methodology suggests achieving accurate software performance estimation at high emulation speed by utilizing a two-phase pipeline scheduling process: a static pipeline scheduling phase performed off-line before runtime, followed by an accuracy refinement phase performed at runtime. The first phase delivers a pre-estimated CPU cycle count while limiting impact on the emulation speed. The second phase refines the pre-estimated cycle count to provide further accuracy. We implemented this methodology on QEMU and compared cycle counts with a physical ARM CPU. Our results show the efficiency of the tradeoffs between emulation speed and cycle accuracy: cycle simulation error averages 10% while the emulation latency is 3.37 times that of original QEMU.

Delay estimation for technology independent synthesis

This paper proposes path mapping, a method of delay estimation for technology independent combinational circuits. Path mapping provides fast and accurate delay estimation using the common ideas of tree covering technology mapping. First, path mapping performs technology mapping for all paths in the circuit with minimum delay. Then, it finds the most critical path among all the paths in the circuit. Finally, it answers its path delay as the circuit delay. Experimental results show path mapping estimates more accurate circuit delay than unit delay, and runs much faster than the technology mapper.

Partitioning-based multiplexer network synthesis for field-data extractors

As seen in packet analysis of TCP/IP offload engine and stream data processing for video/audio data, it is necessary to extract a particular data field from bulk data, where we can use a field-data extractor. Particularly, an (M, N)-field-data extractor reads out any consecutive N bytes from an M-byte register by connecting its input/output using multiplexers. However, the number of required multiplexers increases too much as the input/output byte lengths increase. How to reduce the number of its required multiplexers is a major challenge. In this paper, we propose an efficient multiplexer network synthesis method for an (M, N)-field-data extractor. Our method is based on inserting an (N + B - 1)-byte virtual intermediate register into a multiplexer network and partitioning it into an upper network and a lower network. Our method theoretically reduces the number of required multiplexers without increasing the multiplexer network depth. We also propose how to determine the size of the virtual intermediate register that minimizes the number of required multiplexers. Experimental results show that our method reduces the required number of gates to implement a field-data extractor by up to 92% compared with the one using a naive multiplexer network.

Multi-Level Logic Minimization of Large Combinational Circuits by Partitioning

We developed a top-down partitioning and Boolean minimization method which can be applied to fairly large combinational circuits. The method uses two-way partitioning based on ratio cut algorithm recursively. We got equivalent results for ISCAS85 circuits compared with full.simplfiy [9] and 20-40% reduction of literals for the largest ISCAS89 circuits within 1.5 CPU hours of SPARC2 excluding trivial redundancy, such as inverter chains.

Data-triggered breakpoint for in-circuit debug without re-implementation

In this paper we propose a new breakpoint mechanism, which improves controllability of in-circuit debug. It monitors data packets transmitted on the interface port of the target hardware, and triggers a breakpoint when a specified packet is detected among them in realtime. Regarding a data packet as a series of data sequences, we employ an efficient data sequence matching circuit, which is general purpose and is not restricted to specific protocols or applications. Owing to linearity of CRC (Cyclic Redundancy Check) and co-operation with a software debugger, that matching method is implemented with a simple in-circuit debug module, and achieves at-speed and realtime detection of specified data sequences. Moreover, changing breakpoint conditions does not require hardware re-implementation, but requires just modifying values of data registers inside the debug module. We expect this brings verification operators enormous reduction of both efforts and TAT (Turn-Around-Time) for in-circuit debug. Our experimental results show our proposed method can be implemented in an efficient hardware with small area overheads, and can work with enough accuracy and speed for practical use.