Kaoru Narita

Resonance stub effect in a transition from a through via hole to a stripline in multilayer PCBs

We present results of study of the resonance stub effect occurring in a transition from a through via hole to a stripline in a multilayer printed circuit board (PCB). This effect for via structures including ground vias is estimated by numerical simulations and measurements in the frequency band up to 20 GHz. Ways to alleviate problems in the design of interconnections embedded in multilayer PCBs due to the resonance stub effect and possible applications of the effect in microwave filtering are traced.

An accurate experimental method for characterizing transmission lines embedded in multilayer printed circuit boards

We have developed an accurate method for measuring the complex propagation constant and characteristic impedance of transmission lines embedded in multilayer printed circuit boards. It is based on mathematical error-removal schemes using two different length transmission lines and an advanced via-hole structure that minimizes coupling. Consequently, associated errors, due to discontinuities and interference can be effectively eliminated, and the frequency dependencies of the transmission line parameters can be clarified in wide frequency bandwidths. We verified the validity of this method in frequency ranges up to at least 18 GHz, by comparing the determined values with the theory derived from transverse electromagnetic (TEM) approximations.

A novel on-chip electrostatic discharge (ESD) protection with common discharge line for high-speed CMOS LSIs

A novel on-chip electrostatic discharge (ESD) protection for high-speed CMOS LSIs that operate at higher than 500 MHz has been developed. Introduction of a newly developed common discharge line (CDL) can completely eliminate the protection device influence on the inner circuit operation. This enables minimization of the I/O capacitance by shrinking the dimension of the output transistor, which also serves as a protection device in conventional devices. This new protection (CDL protection) was applied to a high-speed DRAM of which I/O pin capacitance specification is 2 pF. As a result, the ESD tolerance of 4 kV for the charged device model test, 4 kV for the human body model test, and 700 V for the machine model test were obtained. In addition, the DRAM data rate higher than 660 MHz at room temperature was achieved. The results show significant improvement for both ESD and the I/O capacitance, compared with the conventional structure.

A novel on-chip electrostatic discharge (ESD) protection for beyond 500 MHz DRAM

An on-chip electrostatic discharge (ESD) protection for high speed DRAMs that operate at higher than 500 MHz has been developed. Introduction of a newly developed common discharge line (CDL) can completely eliminate the protection device influence on the inner circuit operation. This enables minimization of the I/O capacitance by shrinking the I/O transistor dimension, which acted also as a protection device in the conventional device. As a result, the ESD tolerance of 4 kV for the charged device model (CDM) test, 4 kV for the human body model (HBM) test, and 700 V for the machine model (MM) test were obtained. In addition, a DRAM data rate higher than 660 MHz at room temperature was achieved. The results show significant improvement for both ESD and the I/O capacitance, compared with the conventional structure.