Takanori Saeki

A 2.5 ns clock access 250 MHz 256 Mb SDRAM with a synchronous mirror delay

A 245.7 mm/sup 2/ 256 Mb SDRAM uses: (1) 60.2% cell-occupancy ratio array, (2) prefetched pipeline using first-in first-out buffer with parallel/serial converter, (3) synchronous mirror delay circuit.

A 30-ns 64-Mb DRAM with built-in self-test and self-repair function

A 64 Mw*1 b/16 Mw*4 b DRAM with 30-ns access time which uses a double-metal layer and 0.4- mu m CMOS technology is reported. The external power supply is 3 V, while memory cell arrays operate at 2.2 V. Key circuits for the 64-Mb DRAM are (1) a latched-sense, shared-sense circuit with open bit-line read-out and folded bit-line rewrite operations (LOF) to reduce inter-bit-line coupling noise, (2) alternatively activated and separately end-located word drivers and X decoders to reduce word-line selection delay, and (3) built-in self test and repair circuits using spare memory cells to reduce test costs and increase chip reliability. >

A 30-ns 256-Mb DRAM with a multidivided array structure

A 256-Mb DRAM with a multidivided array structure has been developed and fabricated with 0.25- mu m CMOS technology. It features 30-ns access time, 16-b I/Os, and a 35-mA operating current at a 60-ns cycle time. Three key circuit technologies were used in its design: a partial cell array activation scheme for reducing power-line voltage bounce and operating current, a selective pull-up data-line architecture to increase I/O width and reduce power dissipation, and a time-sharing refresh scheme to maintain the conventional refresh period without reducing operational margin. Memory cell size was 0.72 mu m/sup 2/. Use of the trench isolated cell transistor and the HSG cylindrical stacked capacitor cells helped reduce chip size to 333 mm/sup 2/. >

Resonance stub effect in a transition from a through via hole to a stripline in multilayer PCBs

We present results of study of the resonance stub effect occurring in a transition from a through via hole to a stripline in a multilayer printed circuit board (PCB). This effect for via structures including ground vias is estimated by numerical simulations and measurements in the frequency band up to 20 GHz. Ways to alleviate problems in the design of interconnections embedded in multilayer PCBs due to the resonance stub effect and possible applications of the effect in microwave filtering are traced.

A direct-skew-detect synchronous mirror delay for application-specific integrated circuits

A nonfeedback CMOS digital-clock-generator, direct-skew-detect synchronous-mirror-delay (direct SMD) circuit has been developed that achieves clock-skew suppression in only two clock cycles for application-specific integrated circuits having unfixed and various clock paths. The direct SMD circuit detects both clock skew and clock cycle by using a direct-skew detector and clock-suspension circuitry. The skew-detection scheme removes the phase errors caused by delay in the clock-driver circuit. Measurements demonstrated that the direct SMD circuit eliminates various amounts of clock skew (2.0-3.0 ns) at 200 MHz in two clock cycles.

A 1.3-cycle lock time, non-PLL/DLL clock multiplier based on direct clock cycle interpolation for "clock on demand"

A 1.3-cycle lock-in time, non-PLL/DLL clock multiplier based on direct clock cycle interpolation is proposed with an array structure of short-circuit-current-suppression interpolators. The circuits have been fabricated with a 0.25-/spl mu/m digital CMOS and operated in any condition where digital CMOS circuits operate. Measured results have achieved 1.3 clock cycle lock time and cycle-to-cycle jitter suppression characteristics. The circuits have been verified in 622-Mb/s clock and data recovery that satisfied the ITU-T G.958 jitter tolerance specification.

A 1.3 cycle lock time, non-PLL/DLL jitter suppression clock multiplier based on direct clock cycle interpolation for "clock on demand"

A 1.3-cycle lock time, jitter suppression clock multiplier based on direct clock cycle interpolation uses an array of short-circuit-current-suppression interpolators. The circuits are verified in 622 MHz clock and data recovery satisfying the ITU-T G.958 jitter tolerance specification.

Highly reliable 2.5 nm Ta/sub 2/O/sub 5/ capacitor process technology for 256 Mbit DRAMs

A recently developed capacitor process technology can fabricate highly reliable 2.5 nm equivalent thick Ta/sub 2/O/sub 5/ suitable for the cylindrical stacked capacitor of 256 Mb DRAMs. The capacitor process consists of RTN (rapid thermal nitridation) treatment of native SiO/sub 2/ on the cylindrical stacked polysilicon, RTA (rapid thermal annealing) treatment after Ta/sub 2/O/sub 5/ deposition, and the use of a TiN plate electrode formation on the Ta/sub 2/O/sub 5/ film, TDDB (time-dependent dielectric breakdown) tests showed that the 2.5 nm Ta/sub 2/O/sub 5/ capacitor reliability is as high as 10 years and more for 1/2V/sub cc/=1.0 V/100 degrees C operating conditions.<<ETX>>

A boosted dual world-line decoding scheme for 256 Mb DRAMs

A boosted dual word-line decoding scheme with regulated power supply is developed to realize a memory cell applicable to 256 Mb DRAMs by using silicon dioxide as a dielectric material, and without area increase of the memory cell array. The scheme relaxes the wiring pitch on the cell array, thus making it easier to realize wiring patterns in the large step environment caused by the stack capacitor thickness. A capacitance of up to 50 fF can be realized for a dual cylindrical structure with 1 mu m height and 5 mm oxid thickness. The scheme yields word rising operations two times faster than conventional approaches.<<ETX>>

The direct skew detect synchronous mirror delay (Direct SMD) for ASICs

This paper describes a new concept nonfeedback CMOS digital clock generator, Direct SMD, that achieves clock deskew in only two clock cycles for ASICs having unfixed and various clock paths. The Direct SMD detects clock skew as well as clock cycle by introducing direct skew detector and clock suspension circuitry. The direct skew detection scheme completely removes the phase error caused by the delay fluctuation of the clock driver. The measured results demonstrate that the Direct SMD can successfully eliminate various amounts of clock skew (2.0 ns-3.0 ns) at 200 MHz in two clock cycles.