Karen Kirmse

Mask undercut in deep silicon etch

Mask undercut in the time-multiplexed deep silicon etch process is becoming an increasingly significant issue as it is used to produce smaller critical dimension features. Models of the process must contain the necessary physics to reproduce the dependencies of mask undercut. We argue that the reason undercut develops is the dependence of the deposition step on ion flux. Our experiments of C4F8 (and CHF3 not shown) plasmas show that the film growth is dominantly ion-enhanced. This leads naturally to a mask undercut that increases in time. A more neutral flux dominant deposition step would result in reduced mask undercut.

Spectral scatterometry for 2D trench metrology of low-K dual-damascene interconnect

A systematic study has been conducted to evaluate accuracy and precision of spectral scatterometry used for two-dimensional (2D) characterization of trenches formed in fluorinated silicon glass (FSG). Experiments were done on short-flow dual-damascene Cu interconnect material. Trench critical dimensions (CD) obtained using KLA-Tencors spectral scatterometer were correlated with data collected using CD atomic force microscope (AFM), CD scanning electron microscope (SEM) and transmission electron microscope (TEM). 3 major trench characteristics were analyzed: trench width, trench depth and sidewall angle. Spectral scatterometry demonstrated an excellent correlation (above 0.96) with CD AFM and SEM in tested trench width range of (80-240) nm and trench depth range of (410-450) nm. Spectral scatterometry showed acceptable correlation of 0.55 and minimal offset of 0.05 degrees with AFM in tested sidewall angle range of (87.5-89) degrees. Spectral scatterometry has demonstrated better than 1.0 nm and 0.2 degrees dynamic precision (3s) for both width and height and sidewall angle, respectively. We conclude that KLA-Tencors SpectraCD system is capable of accurate and precise 2D characterization of FSG trenches. We recommend scatterometry as a high throughput and non-destructive metrology for trench linewidth and depth monitoring in low-K dielectric interconnect manufacturing.

Kinetics of the deposition step in time multiplexed deep silicon etches

The time multiplexed deep silicon etch (TMDSE) process is the etch process of choice to make MEMS devices and through wafer vias. It has been used to produce deep trenches and vias at reasonable throughputs. Significant issues remain for the TMDSE process as well as room for improvement even though it has been both experimentally studied and modeled by a wide variety of researchers. This is because it is a highly complex process. Aspect ratio dependencies, selectivity, and the ability to use photoresist masks (instead of SiO2) are examples of remaining issues. The presently obtainable etch rates do not indicate efficient use of the etchant species. In this article, the authors focus on the deposition step in the TMDSE process. While prior research has generally assumed that the deposition step can be adequately modeled as being controlled by a reactive sticking coefficient, they have experimentally examined the deposition step of the process and found that the film growth is dominantly ion-enhanced. The r...

Local CD variation in 65nm node with PSM processes STI topography characterization (I)

How to effectively control the critical dimension (CD) is always a hot topic in photolithography. In 65nm node using phase shift mask (PSM) techniques, any factors related to CD variations should not be ignored without full investigation due to the ever-decreasing CD budget. In this paper, we focus on the local CD variation (LCDV) at the gate level within an area of 200μm x 200μm printed on a 193nm exposure tool. In contrast with AWLV (across wafer line variation) and ACLV (across chip line variation), the more localized LCDV implies that it is more dependent on the following three major factors: i) local wafer flatness mainly dominated by STI (shallow trench isolation) steps after CMP (chemical mechanical polishing); ii) effectiveness of OPC (optical proximity correction) covering all transistors with different geometrical shapes in circuit layout and iii) line edge roughness (LER) and line width roughness (LWR) related to photo and etch processes. Although OPC errors, LER and LWR are also very important, the current discussion will be limited in characterizing the relationship between LCDV and STI step-height (S-H) due to the length limitation. The STI S-H between the active surface and the trench oxide surface always exists due to the different material selectivity in the CMP process. The major gate CD influences from STI S-H are strongly correlated to the different geometrical shapes of transistors in circuits, such as single/multi-finger, wide/narrow, interior/exterior-flare and etc. According to our experiments and simulations from both alt-PSM (alternating PSM) and att-PSM (attenuating PSM) processes, the following important conclusions can be derived. a) The gate CDs in two PSM processes show different sensitivities to STI S-Hs in different geometrical shapes of transistors in circuit layout. The alt-PSM process is more sensitive than the att-PSM, especially for isolate gates. This is a shortcoming for the alt-PSM process in effectively controlling the LCDV. b) STI S-H usually makes the CD larger in both PSM processes, especially for the isolated gates in the alt-PSM process. From our observations, it is generally true that the narrower the transistor width, the higher the gate CD will be. However, CD variation trends in the att-PSM process are not so explicit as observed with alt-PSM. c) One should be very careful when trying to improve the CD uniformity by reducing STI step-height by using a blanket etch back because OPC errors are tightly combined with STI step-heights. d) Improving the STI S-H uniformity is always welcome because it will improve the AWLV. e) The narrow isolated gate is the best CD feature to monitor the interaction of AWLV with STI S-H uniformity.