Karim Arabi

3D VLSI: A Scalable Integration Beyond 2D

As the semiconductor industry faces serious challenges extending the CMOS roadmap, traditional cost reduction benefits that accompanied power/performance/area (PPA) advantages of successive technology nodes have decreased due to a myriad of process integration challenges and increased variability, reliability, power and thermal constraints. 3D integration technologies have been pursued as a potential solution to help integrate more functions within a confined available dimensions of advanced mobile devices. 3D VLSI (3DV) is an emerging 3D integration technology that unlike packaging-driven 3D technologies (e.g., 2.5D, TSV-based 3D, etc.) can deliver orders of magnitude more integration densities due to extremely small sizes of vertical vias. In this paper, we describe the 3DV technology and its current benefits and challenges. We also survey recent literature that show the potential of 3DV to help continue Moores law trajectory beyond 2D.

Low power design techniques in mobile processes

Summary form only given. Low power design techniques and efficient wireless solutions have been critical in enabling mobile computing in a ubiquitous and cost-effective manner. While demand for ubiquitous mobile computing continues to rise thanks to an array of new applications, their power budget remains constant due to thermal budget limits and slow improvement in battery technology. Therefore, mobile computing continues to drive innovation in technologies that will enable new use cases and applications in an energy efficient manner. These solutions span from new computing architecture, low power circuits, improved process technology and novel power management techniques. This presentation covers the latest state-of-the-art low power design solutions for mobile devices.

Leakage power profiling and leakage power reduction using DFT hardware

In a CMOS logic circuit, the leakage power dissipated depends on the state of the design. In this paper we propose a novel technique to use the Q-gating logic that are added to reduce power during shift to also reduce leakage power during functional standby mode of the circuit. First, we propose leakage-aware test (λ-test) vector generation that can be used to profile leakage power consumed by the circuit. This is used to identify blocks that drains excessive standby leakage power. We also propose a new partial Q-gating technique that uses the λ-test to determine the subset of flops that should be gated-off to achieve maximum simultaneous reduction in shift mode dynamic power and standby mode leakage power. A fast, test relaxation and test cube merging algorithm is used for this purpose. Experiments conducted on ISCAS and ITC benchmarks show up to 43.6% reduction in leakage power. For the partial gated design, we obtained up to 15.3% leakage power reduction and up to 6.1×reduction in shift power.

Special session 6C: New topic mixed-signal test impact to SoC commercialization

With the growing presence of analog and mixed-signal blocks in SoC designs, test and validation cost and quality of mixed-signal circuits is taking the spotlight within the semiconductor industry. This is compounded by the fact that recent innovations in digital test have dramatically reduced the cost of testing digital blocks while analog and mixed-signal blocks are still being tested using brute force methods resulting in a growing contribution of analog test cost to the overall SoC test cost. As a result test cost of mixed-signal blocks in an SoC is becoming an inhibiting factor in commercializing cost effective mixed-signal SoCs. The issue is most pronounced in SoCs with power management and RF components. The normalized cost of test per mm2 of mixed-signal blocks is at least 10 higher than digital blocks. It is therefore imperative for the industry to rapidly advance analog test and characterization to the same level of efficiency as digital in order to effectively manage the test cost and quality of mixed signal SoCs. One of the primary problems is that two of the fundamental building blocks of a test strategy are missing: there is nothing equivalent to automatic test-pattern generation for analog, and that is mainly because there is no practical fault model for analog circuits and DFT and BIST are being used for analog circuits but they are custom efforts for each circuit. The lack of a practical fault model is making it impossible to truncate test effeort while guranteeing test quality before silicon production is fully ramped. In this paper, we will discuss major contributing factors to this trend and examine potential solutions to address the issue. Karim Arabis bio: Karim Arabi is Sr. Director, Engineering at Qualcomm where he is responsible for leading DFT and EDA across the company. He held key technical management positions at PMC Sierra and Cirrus Logic. Karim was a founder of Opmaxx, Inc., an innovative startup in analog design and test automation, acquired by Credence. Karims main research interest includes DFT, BIST, low power design, design methodology development and design automation. Karim received his Ph.D. and M.Sc. degrees in Electrical Engineering from Ecole Polytechnique of Montreal and his B.Sc. degree in Elctronics from Tehran Polytechnic.

Brain-inspired computing

As mobile computing becomes increasingly pervasive, so do our expectations of the devices we use and interact with in our everyday lives. We want these devices to be smarter, anticipate our needs, and share our perception of the world so we can interact with them more naturally. The computational complexity of achieving these goals using traditional computing architectures is quite challenging, particularly in a power- or thermal-constrained environment. This talk will review the rise of machine learning and brain-inspired computing and how it is impacting next generation SoC architectures and its technology drivers.

Emerging 3DVLSI: Opportunities and challenges

As the semiconductor industry continues to drive the CMOS scaling roadmap, traditional cost reduction and the accompanied power/performance/area (PPAC) advantages of successive technology nodes are diminishing to a myriad of process integration challenges and increasing variability, reliability, power and thermal constraints. 3D technologies have been explored as potential alternatives to address various system integration needs and to extend the economic scaling roadmap. Among them, 3D VLSI (3DV) technologies emerge as the most plausible candidates. Unlike packaging-driven 3D technologies (e.g., 2.5D, TSV-based 3D, etc.), the emerging 3DV offers over 1000X more vertical connections approaching the same order of magnitude as 2D VLSI vias. Such a high density of vertical interconnects allows us to envision a cost effective 3D system-on-chip (3D SoC) solution that integrates digital, analog, RF, sensors, power etc. into a single chip device, further expand the PPAC roadmap and drive the next wave of semiconductor growth in the emerging markets of internet of everything (IoE), electronic health (eHealth) and electronic medical (eMedic). In this article, we will discuss the 3DV integration opportunities and associated design and technology challenges.