Kendrick Hoy Leong Yuen

Not so fast my friend: is near-threshold computing the answer for power reduction of wireless devices?

In addition to battery life, power is limiting the performance, feature set, and form factor of most mobile communication devices. Many advanced low power techniques have been developed to deal with the problem, however, the cost of these techniques in terms of area, time to market, and quality has to be traded off against the power savings of each. Near threshold Computing (NTC) is a good example of this. NTC is showing great promise as a technique to extend battery life through optimizing energy efficiency. However, the end-users overall experience is still the most important metric and that experience is influenced by performance, response time and battery life; not to mention price. Therefore NTC is limited in its impact to certain mobile products and applications after all the tradeoffs have been considered.

Probabilistically Programmed STT-MRAM

Novel memory programming methods and corresponding memory structures are presented in this paper. Unlike conventional memory programming, this programming technique does not require deterministic switching of memory elements. This technique explicitly exploits the probabilistic switching characteristics of memory elements such as spin-transfer torque magnetic tunnel junction (STT-MTJ) to reduce programming power and delay. This technique also allows multilevel cell (MLC) spin-transfer torque magnetoresistive random access memory (STT-MRAM) to be fabricated with existing STT-MTJ fabrication processes, thus making high capacity STT-MRAM chips readily achievable. The optimal STT-MTJ switching probabilities are given in this paper for reaching minimum programming delay, power, and iteration. Moreover, this paper proves, by applying probabilistic programming to existing STT-MTJs, both programming delay and power can be reduced to levels beyond the reach of conventional deterministic programming. Furthermore arbitrarily small programming bit error rate (BER) can be accomplished in theory using probabilistic programming without much penalty on average programming delay and power. On the contrary, deterministic programming always presents finite programming BER, which is expensive to reduce in terms of programming power and delay. The MLC capability of STT-MTJ clusters has also been confirmed using fabricated STT-MTJ devices. The major circuitries for implementing probabilistically programmed MLC STT-MRAM are also presented in this paper.

Exploiting error-correcting codes for cache minimum supply voltage reduction while maintaining coverage for radiation-induced soft errors.

Models for cache yield and coverage for radiation-induced soft errors quantify the trade-off between the minimum supply voltage (VMIN) and the soft-error protection when applying error-correcting codes (ECC) to a cache. Model predictions of the VMIN benefit and soft-error coverage agree closely with silicon measurements from a 7Mb data cache in a 20nm test chip when considering either single-error correction, double-error detection (SECDED) or double-error correction, triple-error detection (DECTED) codes. Silicon measurements demonstrate a VMIN reduction of 19% and 27% from SECDED and DECTED, respectively, as compared to a cache without ECC. Moreover, silicon measurements highlight a salient insight in that only 0.12% of the cache words contain an error when operating at the cache VMIN with SECDED. Thus, SECDED simultaneously enables a 19% lower VMIN and 99.88% coverage for radiation-induced soft errors. Model projections indicate larger benefits in VMIN and soft-error protection as future cache sizes increase.

Trading-off on-die observability for cache minimum supply voltage reduction in system-on-chip (SoC) processors

Circuit techniques for reducing the minimum supply voltage (V MIN ) of last-level and intermediate static random-access memory (SRAM) caches enhance processor energy efficiency. For the first time at a 16nm technology node, projections of a high-density 6-transistor SRAM bit cell indicate that the VMIN of a 4Mb or larger cache exceeds the maximum supply voltage (V MAX ) for reliability. Thus, circuit techniques for cache VMIN reduction are transitioning from an energy-efficient solution to a requirement for cache functionality. Traditionally, error-correcting codes (ECC) such as single-error correction, double-error detection (SECDED) aim to protect the cache operation from radiation-induced soft errors. Moreover, during the qualification of a system-on-chip (SoC) processor, test engineers monitor the rate of correctable cache errors from SECDED for observing the on-die interactions between integrated components (e.g., CPU, GPU, DSP, etc.). This presentation highlights the opportunity to exploit ECC for reducing the cache V MIN while simultaneously providing coverage for radiation-induced soft errors. Silicon test-chip measurements from a 7Mb data cache in a 20nm technology demonstrate a V MIN reduction of 19% from SECDED. In addition, silicon measurements provide a salient insight in that only 0.12% of the cache words contain an error when operating at the cache V MIN with SECDED. Therefore, SECDED improves V MIN by 19% while maintaining 99.88% coverage for radiation-induced soft errors. In applying SECDED for a lower cache VMIN, the rate of correctable errors exponentially increases, thus eliminating a useful metric for on-die observability. The presentation concludes by offering alternative solutions for on-die observability.