Karl J. L. Geisler

Direct liquid thermal management of 3D chip stacks

Chip stacks are a crucial building block in advanced 3D microsystem architectures and can accommodate shorter interconnect distances between devices, reduced power dissipation, and improved electrical performance. Although enhanced conduction can serve to transfer the dissipated heat to the top and sides of the package and/or down to the underlying PCB, effective thermal management of stacked chips remains a most difficult challenge. Immersion cooling techniques, which provide convective and/or ebullient heat transfer, along with buoyant fluid flow, in the narrow gaps separating adjacent chips, are a most promising alternative to conduction cooling of three-dimensional chip stacks. Application of the available theories, correlations, and experimental data are shown to reveal that passive immersion cooling-relying on natural convection and/or pool boiling — could provide the requisite thermal management capability for 3D chip stacks anticipated for use in much of the portable equipment category. Alternatively, pumped flow of dielectric liquids through the microgaps in 3D stacks, providing single phase and/or flow boiling heat absorption, could meet many of the most extreme thermal management requirements for highperformance 3D microsystems. Use of deionized water is shown to provide an order of magnitude improvement in heat dissipation relative to the available dielectric fluids.

Surface Effects on Confinement-Driven Pool Boiling Enhancement in Vertical Parallel-Plate Channels

Evidence of confinement-driven boiling heat transfer enhancement in vertical channels is very well documented in the literature and much has been observed about its nature and behavior. However, the majority of the available correlations is empirically-based and they tend to be very restricted in their range of applicability and portability. In order to further elucidate the effect of this type of geometrical confinement on boiling heat transfer, an experimental study has been performed on vertical, rectangular parallel-plate channels immersed in the dielectric liquid FC-72. The enhancement of nucleate boiling performance with decreased channel spacing was found to depend on the type of heater employed but could not be explained by the surface roughness. On the other hand, degradation of the Critical Heat Flux (CHF) limit with decreasing channel spacing was found to be independent of the surface and to be well predicted by a correlation available in the literature.Copyright

Numerical and experimental investigations of boiling enhancement in buoyancy-driven microchannels

In this study, confinement-driven boiling enhancement trends and experimental data from narrow parallel plate channels are presented and analyzed via comparison with numerical simulations of buoyancy-driven boiling and two phase flow using the commercially-available Fluent CFD software package. An Euler-Euler multiphase approach, known as the volume of fluid (VOF) method, is employed, as bubbles sizes are on the order of the channel dimensions. Numerical results suggest that enhanced natural convection already accounts for a large portion of the unconfined pool boiling heat flux. While the increased buoyancy from large vapor fractions in narrow channels may lead to an order of magnitude increase in channel mass flux, confinement-driven convective enhancement is found to increase the unconfined boiling heat flux by less than 10%. Further, simulated convective enhancement is found to be a maximum for intermediate size channels, in direct contrast to experimental data which show maximum enhancement (500%) for the smallest channels investigated. Experimental results for different channel wall materials suggest an enhancement mechanism highly dependent on boiling surface characteristics.

Optimization of Pool Boiling Heat Sinks Including the Effects of Confinement in the Interfin Spaces

A finite element analysis approach is developed and used to efficiently evaluate and optimize the boiling performance of longitudinal rectangular plate fin heat sinks, including the explicit dependence of fin spacing on boiling heat transfer coefficients and on the critical heat flux (CHF). Polished silicon heat sinks are shown to dissipate at nearly five times the CHF limit of the unfinned base area and outperform comparable aluminum heat sinks by a factor of 2. For optimum heat sink geometries, over the parameter ranges explored, the fin thickness is found to be approximately equal to the fin spacing, and the relationship between the optimum thickness and spacing is demonstrated to be relatively insensitive to the fin thermal conductivity. Results suggest that even greater performance enhancements may be gained with appropriately-selected advanced materials.

Parametric design of a low-profile, forced convection heat sink for high-power, high-density LED arrays

Solid state light sources, such as light emitting diodes (LEDs), provide many inherent benefits and will dominate the lighting industry in the coming decades. While much of the industry is currently focused on packaging LED technology in standardized 19th century form factors to address the massive installed base of traditional fixtures, the unique characteristics of solid state devices can and will be exploited to produce new luminaire types and new paradigms in lighting design for the 21st century and beyond. Since operating temperatures directly impact energy efficiency, output spectrum, and product lifetime, thermal management is a key linkage in the interdependence of application requirements, design trade-offs, and performance characteristics. This paper details the design of a high-power, high-density LED-based light source for large-scale lighting applications. In particular, a low-profile folded-fin copper heat sink was designed for forced-convection cooling by an array of 38 mm × 38 mm fans. Heat sink dimensions, including fin thickness, fin spacing, heat sink length, and heat sink base thickness to fin height ratio, were varied within form factor constraints and manufacturing limits to produce a suitable thermal solution for a 60,000+ lumen, 50.8 mm × 50.8 mm LED array dissipating 600 W of heat. Results of numerical, analytical, and experimental investigations demonstrate that LED junction temperatures can be maintained below maximum operating limits in a 45°C ambient.

Thermomechanical modeling and evaluation of the impacts of BGA warpage on low-cycle solder fatigue

Given the complex, 3D nature of electronic component geometries, high package assembly temperatures, and the large difference in thermomechanical properties between silicon dies, organic substrates, and package lids or molding compounds, commercial electronic components typically exhibit significant warpage behaviors over temperature. Warpage measurements are presented for various ball grid array (BGA) packages. For these components, warpage behaviors include simple convex or concave in addition to more complex shapes, with zero-warpage temperatures ranging from 180°C to room temperature to sub-room temperature. Results of finite-element-based thermal fatigue analyses for various idealized and increasingly realistic cases demonstrate that package warpage has a larger effect on BGA fatigue than in-plane CTE mismatch between the package and underlying printed circuit board (PCB). While the choice of zero-warpage reference temperature is observed to affect subsequent fatigue life predictions, the magnitude of this effect over a wide range of reference temperature values is less than plus-or-minus 2 percent.

Passive Immersion Cooling of 3-D Stacked Dies

Three-dimensional die stacking increases integrated circuit (IC) density, providing increased capabilities and improved electrical performance on a smaller printed circuit board (PCB) footprint area. However, these advantages come at the expense of higher volumetric heat generation rates and decreased thermal and mechanical access to the die areas. Passive immersion cooling, allowing for buoyancy-driven fluid flow between stacked dies, can provide high heat transfer coefficients directly on the die surfaces, can easily accommodate a wide variety of interconnect schemes, and is scalable to any number of dies. A methodology for the optimization of immersion cooled 3-D stacked dies is presented, including the effects of confinement on natural convection and channel boiling. Optimum die spacings for both single and two phase cooling with saturated FC-72 are found to be on the order of half a millimeter for typical microelectronics geometries and to yield heat densities of 10-50 W/cm3 in natural convection and 100-500 W/cm3 in channel boiling.

THERMAL PERFORMANCE MAPS FOR FORCED AIR COOLING OF RUGGEDIZED ELECTRONICS ENCLOSURES

Based on standard commercial form factors, this study explores chassis-level air cooling limits for ruggedized military electronics enclosures constrained by pressure drop requirements and fin manufacturing capabilities. Numeric and analytic models are developed and used to define a methodology for optimizing the geometry of longitudinal plate fins included in side wall ducts to maximize the amount of heat that can be dissipated from an air-cooled chassis. The results of these analyses are presented in the form of a performance map facilitate the identification of particular fin manufacturing process well-suited for a specified set of mass flow, pressure drop, and heat transfer requirements. Analysis results demonstrate that if isothermal boundaries can be achieved, the heat transfer capacity of the chassis will increase relative to isoflux boundary condition assumptions. As a means to this end, the incorporation of heat pipes into the chassis wall is explored to enhance heat spreading and approach the isothermal limits of heat dissipation in the airflow ducts.© 2007 ASME

Immersion cooling module for military COTS applications

Thermal management needs of the electronics industry continue to be driven by the demand for increased functionality, high heat dissipation and density, component miniaturization, and the reliability benefits of junction temperature reduction and control. In military/aerospace applications, these challenges are exacerbated by harsh environment considerations (e.g. extreme temperatures, shock and vibration, humidity, corrosive surroundings, orientation variations), open standards form factors with defined physical envelopes, and increasing pressure to employ commercial-off-the-shelf (COTS) hardware. Clearly, there exists a need to explore and develop advanced cooling technologies that can meet the anticipated requirements of future military electronic systems. As a means to this goal, card-level passive immersion cooling experiments were performed with gas-saturated FC-72, FC-77, and FC-84 over a range of system pressures to characterize the heat dissipation performance of a VME-size laboratory prototype (233/spl times/160/spl times/18 mm). Chip heat fluxes in excess of 20 W/cm/sup 2/ were achieved while maintaining chip temperatures below 110/spl deg/C. Further, an overall module heat dissipation of 124 W was transferred with 80/spl deg/C module edge temperatures. The thermal performance of the module was limited by the presence of a vapor/air gap and was improved by increased system pressure. Results suggest that FC-84 at 1.5 atm may provide an acceptable compromise between operating pressure, vapor/air space growth, and boiling critical heat flux (CHF) limitations.

44.3: Display Technologies for LED Lighting, Part I: Optical Components

3M Optical Films deliver brightness, energy performance and color enhancement to liquid crystal displays. A key challenge to adapting these technologies to lighting is transforming thin films to three dimensional components. Results highlight new filmbased delivery formats that deliver improved efficiency and light control for both reflective and refractive optics.