Karl Wittig

METHOD OF CONCURRENT MULTIPLE-MODE MOTION ESTIMATION FOR DIGITAL VIDEO

This paper describes a method of motion estimation that determines the optimum prediction mode, along with the resulting motion vectors, as a part of the estimation process. It supports all six prediction modes that are allowed by the Main Profile of the MPEG-2 video coding standard, including the dual-prime modes, for frame and field picture types. If implemented on a processor whose architecture is optimized for the required operations, its computational complexity will not be much greater than that of conventional single-mode motion estimation.

Industry track: adaptive wireless video streaming proxy for home entertainment networks

In this paper, we propose an adaptive wireless video streaming proxy (AWVSP) for distributing broadcast quality video coded using conventional non-scalable MPEG profiles. A fast Rate-Distortion optimized Data Partitioning (RDDP) algorithm is employed to dynamically adapt the data rate of the MPEG video in real-time to sporadically varying wireless channel. A rate-matching algorithm is used to determine the adaptive data rate based on transmission buffer-occupancy. Our simulation results indicate the superior performance of the proposed AWVSP in terms of perceived video quality measured in both PSNR and playback smoothness.

Combined data partitioning and fine granularity scalability for channel adaptive video transmission

Layered video coding is used for adaptive transmission over channels having variable bandwidths. In the two well-known methods of data partitioning (DP) and fine granularity scalability (FGS), a base layer contains essential information and one or more enhancement layers contain fine detail. FGS is continuously scalable above the base layer by successive DCT coefficient bit planes of lower significance, but suffers losses in coding efficiency at low base layer rates. DP, on the other hand, only provides a base partition for header information and low-frequency coefficients and one or more enhancement partitions for higher-frequency coefficients. This results in degraded quality when the enhancement layer is lost but offers performance near single-layer video as the transmission rate approaches the encoding rate. DP is thus suited to bandwidths that vary over a narrow range, whereas FGS performs robustly over a wider range but not as well as single-layer or DP at bandwidths near the full rate. A combination of the two methods can provide higher quality than FGS alone, over a greater bandwidth range than DP alone. This is achieved by using DP on an FGS base layer, which can now have a sufficiently high rate to improve the FGS coding efficiency. Such a combination has been investigated for one form of DP, known as Rate-Distortion optimal Data Partitioning (RDDP), which attempts to provide the best possible base partition quality for a given rate. A method for combining FGS and DP is described, along with expected and computed performances for different rates.

Parallelism in the decoding of MPEG digital video

The rate at which MPEG digital video is decoded depends primarily on the resolutions and the pixel rates of the images that are ultimately displayed. A variety of MPEG decoders is currently available for standard-definition video. Higher-resolution video, such as HDTV, requires much higher decoding rates. The processing speeds needed for these high rates may not be attainable in a decoder that uses conventional digital processing and memory technologies without the use of parallel processing. This will continue to be true even after high-speed decoders become available for HDTV resolutions, as there will be other video applications (e.g., virtual reality, scientific, and medical imaging) for which still higher resolutions are needed. Consequently, higher processing speeds will be required, along with parallel processing. The MPEG decoding algorithm, however, was designed to process an entire picture sequentially, and as such is not well-suited for parallel processing implementations. In this paper, the general problem of parallelism in the decoding of MPEG video is considered, and a simple, efficient method of partitioning it into parallel processes is described.

Effective half-pel motion compensation and estimation scheme for digital video

Half-pel motion compensation, unlike its full-pel counterpart, requires the availability of up to four pixels from the reference picture to generate each compensated pixel. To compensate a 16 X 16 macroblock, a 17 X 17 array of pixels is needed. The number of memory access cycles necessary to process a macroblock, if half-pel motion compensation is employed, is greater than the number otherwise needed by 33, or 13% of the macroblock size. In some motion prediction modes, two 17 X 9 pixel arrays are used, and the number of additional cycles increases to 50, or 20% of the macroblock size. This affects the timing requirements for digital video decoding. In particular, a clock frequency higher than the pixel rate is required, as is buffering for pixel data to convert between the two rates. This paper considers the above problem and presents a method of reference picture memory access that eliminates the additional processing time required for half-pel motion compensation.

Signal Processing And Compensation Electronics For Junction Field-Effect Transistor (JFET) Focal Plane Arrays

A signal processing system has been designed and constructed for a pyroelectric infrared area detector which uses a matrix-addressable JFET array for readout and for on-focal plane preamplification. The system compensates for all offset and gain nonuniformities in and after the array. Both compensations are performed in real time at standard television rates, so that changes in the response characteristics of the array are automatically corrected for. Two-point compensation is achieved without the need for two separate temperature references. This paper describes the focal plane circuitry used to read out the array, the offset and gain compensation algorithms, the architecture of the signal processor, and the system hardware.