Karthik KrishneGowda

System design considerations for a PSSS transceiver for 100Gbps wireless communication with emphasis on mixed signal implementation

Parallel Sequence Spread Spectrum (PSSS) is a physical layer (PHY) baseband technology which is gaining interest for both wireless and wired multi-gigabit communication systems. PSSS is well suited for mixed signal transceiver implementation including channel equalization and allows for a reduction in power dissipation by avoiding high speed data converters. The architecture of a mixed signal baseband processor for 100 Gbps wireless communication is described that reduces the implementation complexity and results in a consequent reduction in power dissipation and chip area.

Towards 100 Gbps Wireless Communication in THz Band with PSSS Modulation: A Promising Hardware in the Loop Experiment

Terahertz frequency band of 0.06 - 10 THz is especially interesting for ultra-high-speed wireless communication to achieve data rates of 100 Gbps or higher. To accommodate this demand, advanced terahertz signal processing techniques need to be investigated. Parallel Sequence Spread Spectrum (PSSS) is a physical layer (PHY) baseband technology that seems to be suited for being used for ultra-high speed wireless communication since the receiver architecture is especially simple and can be implemented almost completely in analog hardware. In this paper, a PSSS modulated signal at a chip rate of 20 Gcps with a spectral efficiency of (only) 1 bit/s/Hz is transmitted using a linearity limited 240 GHz wireless frontend. PSSS transceiver models are realized offline in MATLAB/Simulink. The PSSS transmitter generates the PSSS modulated symbols that are loaded onto an Arbitrary Waveform generator (AWG) and then transmitted using the available 240 GHz wireless frontend. A Digital Storage Oscilloscope (DSO) samples and stores the received signal. The PSSS receiver performs synchronization, channel estimation and demodulation. For a coded data rate of 20 Gbps, an eye opening of 40% and a BER of 5.4·10-5 has been measured. These results are highly promising to achieve data rates of up to 100 Gbps with PSSS modulation using a RF-frontend having higher linear operating range and thus allowing increasing the bandwidth efficiency to 4 b/s/Hz.

Wireless 100 Gb/s: PHY layer overview and challenges in the THz freqency band

There is a continuous increase of bandwidth-demanding services such as ultra HDTV, 3D TV, etc. which will require data rates up to 100-400 Gb/s for short range wireless communication. This paper introduces a novel mixed-mode design where both analog and digital domain design is considered, which helps in the reduction of power consumption. Parallel Sequence Spread Spectrum (PSSS) is used for physical layer (PHY) baseband technology, which considerably alleviates both transmitter and receiver design.

Multi-level 20 Gbit/s PSSS transmission using a linearity-limited 240 GHz wireless frontend

In this paper, we investigate the applicability of parallel sequence spread spectrum (PSSS) modulation in high bandwidth millimeter wave communication systems using a 240GHz monolithic microwave integrated circuit (MMIC) based radio frequency (RF) frontend. The transmitter (Tx) and receiver (Rx) are connected directly via an attenuator in an incoherent back-to-back setup using two independent local oscillator (LO) sources. Although the system was restricted to phase modulated signals due to limited linearity when using conventional modulated signals, a transmission using a multivalent PSSS sequence with a spectral efficiency of 1 bit/s/Hz succeeded thanks to the introduced coding gain. The recovered data is evaluated in terms of eye opening and bit error rate (BER). At a gross data rate of 20 Gbit/s, an eye opening of 40% and a BER of 5.4 × 10-5 were observed.

Simulation of 100 Gbps using Parallel Sequence Spread Spectrum modulation (PSSS) with 240 GHz radio

This paper assesses the impact of the imperfections in radio components on the delay spread and bit error rate (BER) by simulating both analog and digital domains. Parallel Sequence Spread Spectrum (PSSS) is used for physical layer (PHY) baseband technology, which considerably alleviates both transmitter and receiver design. Authors investigate the performance of the PSSS systems using a 240GHz transmitter and receiver radio. In the Mililink project [1] the 240 GHz RF (Radio Frequency) front-end was developed. The RF front-end parameters like e.g. power amplifier, mixer, striplines and low noise amplifier have been used in our baseband simulation models to emulate radio impairment losses. The BER is simulated for the PSSS modulation with several cyclic prefix and spectral efficiencies.

Towards 100 Gbps wireless communication: Investigation of FEC interleavers for PSSS-15 spreading

The main aspect considered in this paper is a comparison of interleaver sizes for convolutional and low-density parity-check codes (LDPC) employed for 100 Gbps wireless communication at 240 GHz with parallel sequence spread spectrum (PSSS). Interleavers required for PSSS-15 and convolutional codes are larger in silicon area than a complete Reed-Solomon decoder. Thus, convolutional codes are not recommended for the targeted application. LDPC codes require 10x smaller interleavers than convolutional codes and seem to be a good choice for the targeted data rate. Alternatively, interleaved Reed-Solomon decoders are proposed. Hard decision RS decoding reduces the size of the targeted forward error correction processor and provides error correction performance not lower than hard decision convolutional codes at the same code rate.

System design of a mixed signal PSSS transceiver using a linear ultra-broadband analog correlator for the receiver baseband designed in 130 nm SiGe BiCMOS technology

Parallel Sequence Spread Spectrum (PSSS) is a physical layer (PHY) baseband technology that is well suited for mixed-signal transceiver implementation for high data rate wireless communication systems. Mixed signal baseband realization allows for easier implementation of the channel equalization function and eliminates the need for high speed data converters. System design and architecture of a mixed signal baseband processor for 100 Gbps wireless communication is described that reduces the implementation complexity and results in a consequent reduction in power dissipation and chip area. An ultra-broadband analog correlator consisting of a four-quadrant multiplier and a fast resettable integrator using only NPN transistors was designed, fabricated, and measured. The correlator circuit is the core component of the receiver baseband. To the best knowledge of the authors, it is the fastest correlator circuit published so far.

100 Gbps Wireless System and Circuit Design Using Parallel Spread-Spectrum Sequencing

Abstract In this article mixed analog/digital signal processing techniques based on parallel spread-spectrum sequencing (PSSS) and radio frequency (RF) carrier synchronization for ultra-broadband wireless communication are investigated on system and circuit level.