J. Christoph Scheytt

An Integrated 0.6–4.6 GHz, 5–7 GHz, 10–14 GHz, and 20–28 GHz Frequency Synthesizer for Software-Defined Radio Applications

We present an integrated frequency synthesizer which is able to provide in-phase/quadrature phase signal over the frequency bands 0.6-4.6 GHz, 5-7 GHz, 10-14 GHz, and in-phase signal over 20-28 GHz for software-defined radio applications. An integrated voltage-controlled oscillator (VCO) with 34% tuning range and a set of high-speed dividers are used to accomplish all the frequencies. To achieve a wide tuning range while keeping a low gain and a low phase noise, the VCO employs digitally controlled sub-bands. The measured PLL phase noise is - 108 dBc/Hz, -121 dBc/Hz, and -135 dBc/Hz at 1 MHz offset for 24 GHz, 4 GHz, and 700 MHz, respectively. Fabricated in a 0.25 μm SiGe BiCMOS process, the synthesizer occupies a chip area of 4.8 mm2. The synthesizer was optimized for reconfigurable base station applications, but can also be used for cognitive radio, radar systems, satellite communication, and high-speed digital clock generation.

A micromachined double-dipole antenna for 122 – 140 GHz applications based on a SiGe BiCMOS technology

This paper presents an on-chip double-dipole antenna by applying micromachining techniques based on a standard SiGe BiCMOS process. It enables the fully integration of millimeter-wave transceiver and antenna into a single chip. A parametric study has been made in simulation which reveals the influence of the key design parameters over the radiation efficiency and directivity. A prototype has been fabricated and measured to verify the design. The measured peak gain is 8.4 dBi at 130 GHz with a simulated efficiency of 60 %. The 3-dB gain bandwidth is 122 – 140 GHz.

220–250-GHz Phased-Array Circuits in 0.13-

This paper describes the design of 220-250-GHz phased-array circuits in 0.13- μm BiCMOS technology. The design aspects of the active and passive devices that are used in the phased-array systems, such as balun, Wilkinson divider, and branch-line coupler, are presented in details. A millimeter-wave vector modulator is designed to support both amplitude and phase control for beam-forming applications. The designed circuits are integrated together to form a four-channel 220-250-GHz phased-array chip. Each channel exhibits 360° phase control with 18 dB of amplitude control. The entire chip draws 167 mA from a 3.3-V supply. The millimeter-wave phase shifting and the low-power consumption makes it ideal for highly integrated scalable beam-forming systems for both imaging, radiometry, and communication applications.

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We present a single-chip fractional-N PLL for space applications. The design employs a high-current charge pump with optimum output biasing and a low-current charge pump for extension of the tuning range. We show that the extension of the tuning range does not increase phase noise and reference spurs. The PLL is tunable from 17.5 GHz to 18.9 GHz, and the phase noise at 1 MHz offset is below −110 dBc/Hz. Since loop bandwidth and phase noise are almost independent of the output frequency, the design is robust against parameter variations with process, voltage, temperature, and ageing.

SiGe BiCMOS Technology

Parallel Sequence Spread Spectrum (PSSS) is a physical layer (PHY) baseband technology which is gaining interest for both wireless and wired multi-gigabit communication systems. PSSS is well suited for mixed signal transceiver implementation including channel equalization and allows for a reduction in power dissipation by avoiding high speed data converters. The architecture of a mixed signal baseband processor for 100 Gbps wireless communication is described that reduces the implementation complexity and results in a consequent reduction in power dissipation and chip area.

An Integrated 18 GHz fractional-N PLL in SiGe BiCMOS technology for satellite communications

A millimeter wave frequency mixed-signal design of a 1-tap half-rate look-ahead decision feedback equalizer for 80 Gb/s short-reach optical communication systems is presented. On-wafer tests are developed to determine the maximum operating bit rate of the equalizer. Results are also presented for intersymbol interference mitigation at 80 Gb/s for a 20 GHz bandwidth-limited channel. Further improvements on the architecture of the 80 Gb/s equalizer are discussed and used in the design and on-wafer measurement of a 110 Gb/s equalizer. The equalizers are designed in a 0.13 μm SiGe:C BiCMOS technology. The 80 and 110 Gb/s versions dissipate 4 and 5.75 W, respectively and occupy 2 and 2.56 mm2, respectively.

System design considerations for a PSSS transceiver for 100Gbps wireless communication with emphasis on mixed signal implementation

Design of a 40 Gb/s VCSEL driver IC capable of providing up to 10mA current to common-cathode VCSELs is presented. Using low-power bandwidth enhancement techniques, a prototype IC is successfully developed in 180-GHz SiGe BiCMOS technology. Measured results show 34 GHz of bandwidth, open eye diagram with rise/fall time below 10 ps, and power dissipation of 130 mW.

Design and Measurement Techniques for an 80 Gb/s 1-Tap Decision Feedback Equalizer

Terahertz frequency band of 0.06 - 10 THz is especially interesting for ultra-high-speed wireless communication to achieve data rates of 100 Gbps or higher. To accommodate this demand, advanced terahertz signal processing techniques need to be investigated. Parallel Sequence Spread Spectrum (PSSS) is a physical layer (PHY) baseband technology that seems to be suited for being used for ultra-high speed wireless communication since the receiver architecture is especially simple and can be implemented almost completely in analog hardware. In this paper, a PSSS modulated signal at a chip rate of 20 Gcps with a spectral efficiency of (only) 1 bit/s/Hz is transmitted using a linearity limited 240 GHz wireless frontend. PSSS transceiver models are realized offline in MATLAB/Simulink. The PSSS transmitter generates the PSSS modulated symbols that are loaded onto an Arbitrary Waveform generator (AWG) and then transmitted using the available 240 GHz wireless frontend. A Digital Storage Oscilloscope (DSO) samples and stores the received signal. The PSSS receiver performs synchronization, channel estimation and demodulation. For a coded data rate of 20 Gbps, an eye opening of 40% and a BER of 5.4·10-5 has been measured. These results are highly promising to achieve data rates of up to 100 Gbps with PSSS modulation using a RF-frontend having higher linear operating range and thus allowing increasing the bandwidth efficiency to 4 b/s/Hz.

40 Gb/s VCSEL driver IC with a new output current and pre-emphasis adjustment method

Parallel Sequence Spread Spectrum (PSSS) is a physical layer (PHY) base band technology. It was selected for the wireless sensor network standard IEEE802.15.4-2006, in order to increase data rate and radio performance in fading channels for frequency bands below 1GHz. In the work presented in this paper PSSS is used for the first time in the 60 GHz ISM Band to achieve ultra-high transmission speed similar to IEEE802.11ad but at lower receiver complexity. A different encoding scheme than for IEEE802.15.4-2006 has been applied to improve the coverage range of the 60 GHz radio. Using an available 60GHz heterodyne radio we achieved a measured data rate of 4Gb/s at a distance of 3 m using a simple Vivaldi antenna. The signal processing was performed off-line using a Matlab implementation in a “Hardware in the Loop” approach. Furthermore we will outline the architecture of a mixed-signal (analog/digital) baseband processor that reduces the implementation complexity by at least one order of magnitude. This will result both in lower power dissipation as well as lower Silicon area consumption.

Towards 100 Gbps Wireless Communication in THz Band with PSSS Modulation: A Promising Hardware in the Loop Experiment

There is a continuous increase of bandwidth-demanding services such as ultra HDTV, 3D TV, etc. which will require data rates up to 100-400 Gb/s for short range wireless communication. This paper introduces a novel mixed-mode design where both analog and digital domain design is considered, which helps in the reduction of power consumption. Parallel Sequence Spread Spectrum (PSSS) is used for physical layer (PHY) baseband technology, which considerably alleviates both transmitter and receiver design.