Kartik Kalia

Pseudo open drain IO standards based energy efficient solar charge sensor design on 20nm FPGA

In this paper an approach is made to design Pseudo open drain IO standards Based Energy efficient solar charge sensor design on 20nm and 28nm technology. We have used LVCMOS18, POD10, POD10_DCI and POD12 I/O standard. In this design, we have taken two main parameters for analysis that are frequencies (GHz) and AIRFLOW. We have taken one value for LFM i.e. 250 and Medium as a default profile for heat sink and constant environment. For the simulation of the logic, Xilinx is used with Verilog as hardware description language. We have done our analysis for different frequency values for POD based solar charge inverter. We also observed maximum total power reduction in LVCMOS18 (Artix-7 FPGA) as compared to other I/O standards at 10 GHz. Also there is maximum total power reduction in POD12 (Ultra Scale Kintex) as compared to other I/O standards at 2 GHz. There is also a significant change in device static, I/O power and Clock Power.

SSTL based thermal and power efficient RAM design on 28nm FPGA for spacecraft

In this paper, an approach is made to design a Thermal and Power efficient RAM for that reason we have used DDR4L memory and six different members of SSTL I/Os standards on 28nm technology. Every spacecraft requires most energy efficient electronic system and for that very purpose we have designed the most energy efficient RAM. In this design, we have taken two main parameters for analysis that is frequency (1600 MHz) and Voltage (1.05V). DDR4L operates at the lowest Voltage compared to available RAMs. Environment (LFM, Heat Sink, and Capacitance) is kept constant. For the simulation of the logic, Xilinx is used with Verilog as hardware description language. We have done our analysis with different I/O standards for DDR4L RAM. When we scale down from 288.15K to 348.15K there is maximum total power reduction in SSTL135_R as compared to all considered I/O standards. When we compared different members of SSTL for different temperatures and I/O power we observed maximum thermal efficiency in SSTL135_R at minimum and maximum temperature as compared to all other considered I/O standards. When we scale down from 348.15K to 288.15K there is no power reduction in Clock power, Logic power, Signal power, BRAMs and I/Os power respectively.

GTL based wireless sensor specific energy efficient ALU design on 65nm FPGA

This paper consists of design based on sustainable energy efficient ALU32Bit and for that reason we have used four different members of GTL IO standards on 65nm technology. In this paper, we have considered two main parameters for analysis that are frequencies in GHz and AIRFLOW (LFM 250). We have considered Medium as a default profile for heat sink and environment is constant. Xilinx is used for the simulation of logic with Verilog as hardware description language. We have done our analysis for different frequency values for WLANs based on IEEE 802.11 standards. When we scale down from 60GHz to 0.9 GHz we observed maximum IO power reduction and leakage power reduction in GTL, constant clock power and logic power reduction in all the considered IO standards and maximum Signal power reduction in GTLP_DCI and GTL_DCI.