Katarina Boustedt

GHz flip chip-an overview

The drive in industry towards more and more wireless communication for various purposes increases the need for packaging for ever higher frequencies. This paper gives an overview of recent activities, presented by companies and universities, at GHz frequencies. The main topic is the chip interconnect, and GaAs flip chip specifically, Flip chip offers some very significant advantages over wire bonding, such as better electrical performance and smoother assembly process. This makes way for lower production costs and allows for low cost high volume production of both consumer and other products. For lower frequencies, this is well documented, and an increase in activity for high frequencies is now seen. If one is to judge by the number of papers presented, it seems that most of the activities are in USA, Europe, and Asia. In Europe, Germany presents the most results, and in Asia, various Japanese companies dominate. However, it is likely that most of the well known telecom and radar companies are actively investigating flip chip for high frequencies, without presenting the results. Papers are mostly concerned with chip design issues, and simulations of various structures. The coplanar chip design appears to be favored, along with non-melting bumps for interconnect.

High gain active microstrip antenna for 60 GHz WLAN

A 60 GHz design comprising a three-stage pHEMT amplifier integrated with a high gain antenna on an alumina substrate is presented. The amplifier has 18 dB gain, and the antenna a directivity of 14 dBi. The amplifier is ribbon bonded to the substrate on which the antenna is etched. The antenna is a microstrip array antenna with a simple etched pattern for producibility at high frequencies. Mechanical simplicity is achieved with this design, and unnecessary transitions are avoided.

GHz flip chip interconnect experiments

The flip chip is recognized as the most reliable chip interconnect method and renders an extremely high production yield at very low cost. Furthermore, flip chip gives extraordinary electrical performance, which is vital at GHz frequencies. The flip-chip interconnect is based on three fundamental elements, bumps on a die, chip carrier and the method of joining a die to a carrier. These elements are interdependent, thus important to consider each in order to select the optimal flip-chip system for a specific application. The tentative use of an encapsulant is another consideration. Most obviously, the gold pad and conductor metallurgy of GaAs chips bring the need for alternate bumping methods. Two different joining schemes tentatively suitable for GaAs chip pad metallurgies were tested based on thermocompression joining. Bumps were applied to the chip carrier, a thin film substrate and were either plated gold cylinders or gold ball bond studs. Cross-sections, shear tests, and X-ray imaging were used to determine the joint quality.

A new concept for microwave MCMs

The drive in the industry towards smaller, lighter, more efficient products encompasses all types of products, including microwave communication. At Ericsson Microwave Systems, customer demand for a product which integrates the microwave control unit with the antenna in the mast has been noted. This means that the indoor control units become redundant and there is less hardware. This packaging concept is based on the fact that the electronics are placed behind the flat antenna unit for efficient use of the available area. The technical concept is a multilayer PTFE thermoplastic motherboard design and split-function MCMs with possibilities for buried capacitors etc. The chip environment is split between the MCM and the motherboard. The motherboard has shielded conductors and a common ground plane with the MCM. The chips are placed level with the substrate to which they are connected with bond wires, and therefore the wires can be made shorter than if the chips were placed on the board as in ordinary chip and wire cases. The reduced wire length is most significant in order to achieve good electrical performance. To meet market demand, we have designed an electronics packaging system for multi-frequency purposes, for products ranging from 5-40 GHz. Current antenna integrated electronics are mostly military applications designed in exclusive materials for advanced production methods. On entering a market for commercial applications, new methods must be implemented to reach cost-effective targets. This paper presents some possible methods for reaching this goal.

Low-cost E-band flip-chip assembly and materials

By extending the wireless backhaul network to higher frequencies, more bandwidth is available, enabling the higher capacity microwave radio links, to accommodate the increase in traffic from, for example, data use in smartphones. Products for the E-band (specifically 71-76, 81-86, and 92-95 GHz) are now on the market, and, as always, there is a drive for reducing cost, both in manufacturing and sourcing, while maintaining high performance. This paper describes in detail the incoming material and assembly process for E-band GaAs flip chips with lead-free solder, using high volume manufacturing equipment. The choice of incoming materials such as chips, chip carriers, flux and underfill is discussed, and future paths indicated. The target is to take manufacturing processes and materials typically used in consumer products and employ them in millimeter wave products as far as possible. A first assembly round using daisy chain and transmission line test chips mounted on hardback boards with teflon top layer has proven successful, with very high yield in assembly but some problems remaining related to printed circuit board quality.

Dense WDM-PON with 23(46) Gb/s/λ D(Q)PSK aggregation in the feeder and micro-ring resonator assisted ONUs

An aggregation scheme based on a D(Q)PSK/ASK comb transmission in the feeder is presented. A shared delay interferometer allows simple ONUs that are assisted by a ring resonator.

Large-scale photonic integration: a key-enabling technology for all-optical signal processing

Emerging services and applications—such as 3D TV, video on demand, and peer-to-peer applications—are driving network capacity and cost to their limit. Current research and standardization efforts are focusing on the use of advanced modulation formats such as differential-phase-shift keying (DPSK) and differential-quadrature-phase-shift keying (DQPSK) to increase optical-fiber bandwidth capacity. For the foreseeable future, these advanced modulation formats will have to co-exist with standard on-off keying (OOK) due to already-installed fibertransmission equipment. In this context, photonic integration is a key enabling technology toward the aggregation of complex functionalities for multiple modulation formats on single photonic chips. One such initiative is supported by the European Commission through the ICT-APACHE project.1 It aims to develop multi-format transmitters, receivers, and regenerators based on hybrid integration of high-performance indium phosphide (InP) monolithic elements on low-loss planar silica-on-silicon circuits. Hybrid integration has numerous advantages, such as low loss and power consumption, and a small footprint. However, the most significant benefit is easy adaptation of the silica motherboard to different circuit designs and a wide range of applications. Here, we describe a multi-format-processing chip (MFPC) that we fabricated for the first demonstration of multi-format regeneration and wavelength conversion on a single device.2 Until now, this Figure 1. (a) Multi-format-processing-chip (MFPC) layout and (b) mask design. (c) The silica motherboard. The white arrow indicates the position of the quad semiconductor optical amplifier (SOA) array. A–O: Integrated thermo-optic phase shifters. DI: Delay interferometer.