Katarzyna Radecka

Echo cancellation in IP networks

Voice transmission over IP networks imposes new DSP challenges. Package loss and latency caused by packet buffering have the fundamental influence on the speech quality. These features have also an impact on the line echo canceller (EC) performance. The constant latency greater than 60 milliseconds usually causes that an echo is very well audible even for a short echo path delay. Therefore, the EC must be deployed on each 2-wire/4-wire connection while on a conventional transmission only toll connections require EC. Such a large total delay requires short convergence time and sufficient Echo Return Loss Enhancement (ERLE). Further, package loss that is related to non-stationary intervals of speech imposes stringent requirements on EC performance in tracking statistical variations of the signal. Overally, IP telephony requires more robust and less expensive EC than conventional networks. In this paper we address the basic design issues in the EC for IP telephony. We show that classical Least Mean Square (LMS) algorithms are rather inappropriate and offer an alternative solution.

Architectures of increased availability wireless sensor network nodes

Wireless sensor networks (WSNs) are being increasingly used in applications where low energy consumption and low cost are the overriding considerations. With increased use, their reliability, availability and serviceability need to be addressed from the outset. Conventional schemes of adding redundant nodes and incorporating reliability in control protocols can effectively improve only the reliability of the overall WSN. The availability and serviceability of WSN nodes can be addressed by providing the remote testing and repair infrastructure for the individual sensor nodes that is well matched with existing on-board test infrastructure, including standard JTAG chains. We propose and evaluate scalable architectures of WSN nodes for increased availability as well as implement the proposed solutions using COTS components.

FPGA emulation of quantum circuits

Quantum computing offers immense speedup in performing tasks such as data encryption and searching. The quantum algorithms can be modeled using classical computing devices, however classical computer simulations cannot deal efficiently with the parallelism present in quantum algorithms. The quantum circuit model for quantum algorithms is sufficient to describe the known quantum algorithms. Using analogies between quantum and digital circuits, we design the emulator of quantum algorithms in FPGAs that allows efficient experimentation with new quantum algorithms. This paper concentrates on new techniques for modeling quantum circuits, including the entanglement and probabilistic computing realization, as well as the critical issues in the required precision of computing.

Using arithmetic transform for verification of datapath circuits via error modeling

In this paper, we consider verification under error-model assumption. We exploit the algebraic properties of the arithmetic transforms that are used in compact graph-based representations of arithmetic circuits, such as *BMDs. Verification time can be shortened under the assumption of corrupting a bounded number of transform coefficients. Bounds are derived for a number of test vectors, and the vectors successfully verified arithmetic circuits under a class of error models derived from recently proposed basic design error classes, including single stuck-at faults.

A Medical Cloud-Based Platform for Respiration Rate Measurement and Hierarchical Classification of Breath Disorders

The measurement of human respiratory signals is crucial in cyberbiological systems. A disordered breathing pattern can be the first symptom of different physiological, mechanical, or psychological dysfunctions. Therefore, a real-time monitoring of the respiration patterns, as well as respiration rate is a critical need in medical applications. There are several methods for respiration rate measurement. However, despite their accuracy, these methods are expensive and could not be integrated in a body sensor network. In this work, we present a real-time cloud-based platform for both monitoring the respiration rate and breath pattern classification, remotely. The proposed system is designed particularly for patients with breathing problems (e.g., respiratory complications after surgery) or sleep disorders. Our system includes calibrated accelerometer sensor, Bluetooth Low Energy (BLE) and cloud-computing model. We also suggest a procedure to improve the accuracy of respiration rate for patients at rest positions. The overall error in the respiration rate calculation is obtained 0.53% considering SPR-BTA spirometer as the reference. Five types of respiration disorders, Bradapnea, Tachypnea, Cheyn-stokes, Kaussmal, and Biots breathing are classified based on hierarchical Support Vector Machine (SVM) with seven different features. We have evaluated the performance of the proposed classification while it is individualized to every subject (case 1) as well as considering all subjects (case 2). Since the selection of kernel function is a key factor to decide SVMs performance, in this paper three different kernel functions are evaluated. The experiments are conducted with 11 subjects and the average accuracy of 94.52% for case 1 and the accuracy of 81.29% for case 2 are achieved based on Radial Basis Function (RBF). Finally, a performance evaluation has been done for normal and impaired subjects considering sensitivity, specificity and G-mean parameters of different kernel functions.

Analytical Optimization of Bit-Widths in Fixed-Point LTI Systems

Analyses of range and precision are important for high-level synthesis and verification of fixed-point circuits. Conventional range and precision analysis methods mostly focus on combinational arithmetic circuits and suffer from major inefficiencies when dealing with sequential linear-time-invariant circuits. Such problems mainly include inability to analyze precision when quantization of constant coefficients is taken into account, and lacking efficient word-length optimization algorithms to handle both variables and constants, while satisfying the error metrics. The algorithms presented in this paper solve these problems. Experiments illustrate the efficiency and robustness of our algorithms.

Design verification by test vectors and arithmetic transform universal test set

We investigate methodology for simulation-based verification under a fault model. Since it is currently not feasible to describe a comprehensive explicit model of design errors, we propose an implicit fault model. The model is based on the arithmetic transform (AT) spectral representation of faults. The verification of circuits under the small errors in spectral domain is then performed by the universal test set (UTS) approach to test vector generation. The major result shows that, for errors whose AT has at most t nonzero coefficients, there exist the UTS test vector set of size O(n/sub 2//sup log t/). Consequently, verification confidence can be parameterized by the size of the error t, where at most O(n/sub 2//sup log t/) verification vectors are simulated to verify the absence of faults belonging to such an implicitly defined fault class. The experimental confirmation of the feasibility of verification using such UTS is presented, together with the relations between the arithmetic and Walsh-Hadamard spectra that bound the AT error spectrum and show that a class of small error circuits has small error spectrum. The proposed approach has the advantage of compatibility with formal verification and testing methods.

On the Fixed-Point Accuracy Analysis and Optimization of Polynomial Specifications

Fixed-point accuracy analysis and optimization of polynomial data-flow graphs with respect to a reference model is a challenging task in many digital signal processing applications. Range and precision analysis are two important steps of this process to assign suitable integer and fractional bit-widths to the fixed-point variables and constant coefficients in a design such that no overflow occurs and a given error bound on maximum mismatch (MM) or mean-square-error (MSE) and signal-to-quantization-noise ratio (SQNR) is satisfied. This paper explores efficient optimization algorithms based on robust analyses of MM and MSE/SQNR for fixed-point polynomial data-flow graphs. Experimental results illustrate the robustness of our analyses and the efficiency of the optimization algorithms compared to previous work.

Arithmetic Transforms of Imprecise Datapaths by Taylor Series Conversion

We develop a new method to compute representations of imprecise datapaths for purpose of equivalence checking and component matching. From a Taylor series, we devise an efficient algorithm to produce arithmetic transform (AT) which is a function representation behind word-level decision diagrams such as BMDs. Also, we introduce an efficient algorithm for verifying the imprecise circuits.

Scaling and Better Approximating Quantum Fourier Transform by Higher Radices

Quantum Fourier transform (QFT) plays a principal role in the development of efficient quantum algorithms. Since the number of quantum bits that can be built is limited, while many quantum technologies are inherently three (or more) valued, we consider extending the reach of the realistic quantum systems by building a QFT over ternary quantum digits. Compared to traditional binary QFT, the q-valued transform improves approximation properties and increases the state space by a factor of (q/2)n. Further, we use nonbinary QFT derivation to generalize and improve the approximation bounds for QFT