Katerina Raleva

Modeling Thermal Effects in Nanodevices

In order to investigate the role of self-heating effects on the electrical characteristics of nanoscale devices, we implemented a 2D Monte Carlo device simulator that includes the self-consistent solution of the energy balance equations for both acoustic and optical phonons. The acoustic and optical phonon temperatures are fed back into the electron transport solver through temperature-dependent scattering tables. The electrothermal device simulator was used in the study of different generations of nanoscale fully depleted silicon-on-insulator devices that are either already in production or will be fabricated in the next five to ten years. We find less degradation due to self-heating in very short channel device structures due to the increasing role of nonstationary velocity-overshoot effects which are less sensitive to the local temperature.

Self-Heating Effects in Nanoscale FD SOI Devices: The Role of the Substrate, Boundary Conditions at Various Interfaces, and the Dielectric Material Type for the BOX

In this paper, we continue our investigations on self-heating effects in nanoscale fully depleted (FD) silicon-on-insulator (SOI) devices with emphasis on what is the appropriate simulation domain needed for accurate modeling. In that context, we examine the influence of the underlying substrate on the current degradation in the active channel region and what needs to be the proper boundary conditions at the source/drain and gate contacts and the artificial-side boundaries. We finally examine the self-heating effect when the BOX is made of SiO 2, diamond, and AlN. As such, this paper helps one estimate the minimum and the maximum limits on-current degradation due to self-heating effects in FD SOI devices.

Is SOD Technology the Solution to Heating Problems in SOI Devices

In this letter, we present our investigations on heating effects in Si on diamond and Si on AlN transistors, using a coupled Monte Carlo/thermal moment expansion simulator. Both technologies are considered viable alternatives to silicon-on-insulator devices due to the fact that diamond and AlN have significantly higher thermal conductivities than SiO2. This fact is beneficial in the following two aspects, as demonstrated in this letter: (1) It leads to a significant reduction in the thermal degradation of the device electrical characteristics, and (2) it allows a more uniform distribution of temperature in the device active region, which, in turn, enhances heat removal.

Electrothermal Studies of FD SOI Devices That Utilize a New Theoretical Model for the Temperature and Thickness Dependence of the Thermal Conductivity

In this brief, we report on the effects of the spatial and temperature dependence of the thermal conductivity in thin Si films on the electrothermal simulation of nanoscale silicon-on-insulator (SOI) devices. The electrothermal simulator is based on a combined ensemble Monte Carlo device simulator coupled to moment expansion of the phonon Boltzmann transport equations. In particular, we account for boundary scattering and the finite thickness of the SOI layer in reducing its thermal conductivity. The reduced thermal conductivity leads to a higher hot spot temperature in the device, with a corresponding degradation of the source-drain current.

Experimental validation of self-heating simulations and projections for transistors in deeply scaled nodes

CMOS device improvements have recently been achieved by changing the geometry of the device from planar to fully-depleted (FD) FinFET. Also FD SOI (Silicon-on-Isolator) devices have emerged as a candidate for replacing bulk silicon in ULSI applications in future technology nodes. Along with this scaling comes, however, a challenging penalty: device self-heating. In this study, i) we propose a unique measurement technique for self-heating and use it to assess self-heating in planar devices, ii) we compare and verify these results with finite-element simulations and iii) we provide perspectives for upcoming FinFET nodes.

Characterization of self-heating in high-mobility Ge FinFET pMOS devices

Based on physically-extended methodology, measurements and simulations show that implementing high-mobility materials and particularly alloys, such as a SiGe buffer for mobility enhancement in a Ge channel, can result in a 115% increase in self heating in the N7 node, compared to standard Si FinFETs.

Heating Effects in Nanoscale Devices

The ever increasing demand for faster microprocessors and the continuous trend to pack more transistors on a single chip has resulted in an unprecedented level of power dissipation, and therefore higher temperatures at the chip level. Thermal phenomena are not directly responsible for the electrical functionality and performance of semiconductor devices, but adversely affect their reliability. Four major thermally-induced reliability concerns for transistors are: (1) degradation of device thermal characteristics due to heating effects, (2) failure due to the electrostatic discharge phenomenon, (3) stresses due to different rates of thermal expansion of transistor constituents, and (4) failure of metallic interconnects due to diffusion or flow of atoms along a metal interconnect in the presence of a bias current, known as the electromigration phenomenon. Self-heating of the device and interconnects reduces electron mobility and results in a poor or, at best, non-optimal, performance of these devices and structures. Fig. 1 shows the trend of the average power density for high-performance microprocessors according to the ITRS. No flattening or slower decelerated increase will occur after the introduction of the Silicon on Insulator (SOI) technology. It should be noted that the power density shown in Fig. 1 is the average power density, i.e. the total chip power divided by the chip area. In logic circuits, such as microprocessors, the power is non-uniformly distributed. There are portions of the chip of quite low power dissipation (memory blocks) and, on the other hand, portions running at full speed with high activity factors where the power density can easily be more than a magnitude higher than the average chip power density from Fig. 1. The latter portions will create hot spots with quite high local temperature. The power density in the active transistor region (essentially the channel region underneath the gate) is again much higher than the average power density in a hot spot when the transistor is in the on-state. Thus, the treatment of self-heating and the realistic estimation of the power density is quite a complex problem. Sometime within the next five years, traditional CMOS technology is expected to reach limits of scaling. As channel lengths shrink below 22 nm, complex channel profiles are required to achieve desired threshold voltages and to alleviate the short-channel effects. To fabricate devices beyond current scaling limits, Integrated Circuits (IC) companies are simultaneously pushing planar, bulk silicon CMOS design while exploring alternative gate stack materials (high-k dielectrics and metal gates), band engineering methods (using 3

Monte Carlo Device Simulations

As semiconductor devices are scaled into nanoscale regime, first velocity saturation starts to limit the carrier mobility due to pronounced intervalley scattering, and when the device dimensions are scaled to 100 nm and below, velocity overshoot starts to dominate the device behavior leading to larger ON-state currents. Alongside with the developments in the semiconductor nanotechnology, in recent years there has been significant progress in physical based modeling of semiconductor devices. First, for devices for which gradual channel approximation can not be used due to the two-dimensional nature of the electrostatic potential and the electric fields driving the carriers from source to drain, driftdiffusion models have been exploited. These models are valid, in general, for large devices in which the fields are not that high so that there is no degradation of the mobility due to the electric field. The validity of the drift-diffusion models can be extended to take into account the velocity saturation effect with the introduction of field-dependent mobility and diffusion coefficients. When velocity overshoot becomes important, drift diffusion model is no longer valid and hydrodynamic model must be used. The hydrodynamic model has been the workhorse for technology development and several high-end commercial device simulators have appeared including Silvaco, Synopsys, Crosslight, etc. The advantages of the hydrodynamic model are that it allows quick simulation runs but the problem is that the amount of the velocity overshoot depends upon the choice of the energy relaxation time. The smaller is the device, the larger is the deviation when using the same set of energy relaxation times. A standard way in calculating the energy relaxation times is to use bulk Monte Carlo simulations. However, the energy relaxation times are material, device geometry and doping dependent parameters, so their determination ahead of time is not possible. To avoid the problem of the proper choice of the energy relaxation times, a direct solution of the Boltzmann Transport Equation (BTE) using the Monte Carlo method is the best method of choice. That is why the focus of this review paper is on explaining basic Monte Carlo device simulator and then the focus will be shifted on the inclusion of various higher order effects that explain particular physical phenomena or processes. The Monte Carlo book chapter is organized as follows. First, the idea behind the Monte Carlo technique is outlined by revoking the path integral method for the solution of the BTE. This approach naturally leads to the free-flight-scatter sequence that is used in solving the BTE using the Monte Carlo method. Various scattering mechanisms relevant for different

Uncovering the temperature of the hotspot in nanoscale devices

We present for the first time multi-scale modeling of self-heating effects in conventional MOSFET devices in a common-source and common-drain configurations in which one of the devices is the device under test (DUT) and the other device is the sensor. Via comparisons to experimental measurements performed at IMEC, we are able to uncover the temperature of the hot spot. This is also the first study in which a circuit with two transistors is being simulated using thermal particle-based device simulations.

Is self-heating important in nanowire FETs?

In this work we investigate self-heating effects in nanowire FETs. We find that, as in the case of FD SOI devices, the velocity overshoot effect of the carriers in the channel and reduced number of scattering events with phonons lead to smaller ON-current degradation in short compared to long channel nanowire transistors.