Kathleen Philips

A 10.7 MHz IF-to-baseband /spl Sigma//spl Delta/ A/D conversion system for AM/FM radio receivers

/spl Sigma//spl Delta/ modulation with integrated quadrature mixing is used for analog-to-digital (A/D) conversion-of a 10.7-MHz IF input signal in an AM/FM radio receiver. After near-zero IF mixing to a 165 kHz offset frequency, the I and Q signals are digitized by two fifth-order, 32 times oversampling continuous-time /spl Sigma//spl Delta/ modulators. A prototype IC includes digital filters for decimation and the shift of the near-zero-IF to dc. The baseband output signal has maximum carrier-to-noise ratios of 94 dB in 9 kHz (AM) and 79 dB in 200 kHz (FM), with 97 and 82 dB dynamic range, respectively. The IM3 distance is 84 dB at full-scale A/D converter input signal. Including downconversion and decimation filtering, the IF A/D conversion system occupies 1.3 mm/sup 2/ in 0.25-/spl mu/m standard digital CMOS. The /spl Sigma//spl Delta/ modulators consume 8 mW from a 2.5-V supply voltage, and the digital filters consume 11 mW.

A continuous-time /spl Sigma//spl Delta/ ADC with increased immunity to interferers

Receivers are being digitized in a quest for flexibility. Analog filters and programmable gain stages are being exchanged for digital processing at the price of a very challenging ADC. This paper presents an alternative solution where the filter and programmable gain functionality is integrated into a /spl Sigma//spl Delta/ ADC. The novel filtering ADC is realized by adding a high-pass feedback path to a conventional /spl Sigma//spl Delta/ ADC while a compensating low-pass filter in the forward path maintains stability. As such, the ADC becomes highly immune to interferers even if they exceed the maximum allowable input level for the wanted channel. As a consequence, the ADC input range can be programmed dynamically to the level of the wanted signal only. This results in an input-referred dynamic range of 89 dB in 1-MHz bandwidth and an intentionally moderate output signal-to-noise-and-distortion ratio of 46-59 dB (depending on the programmed gain). The merged functionality enables a better overall power/performance balance for the receiver baseband. The design consumes less than 2 mW and active area is 0.14 mm/sup 2/ in a 0.18-/spl mu/m digital CMOS technology.

A 3.3mW /spl Sigma//spl Delta/ modulator for UMTS in 0.18/spl mu/m CMOS with 70dB dynamic range in 2MHz bandwidth

A quadrature fourth-order, continuous-time, modulator with 1.5-b quantizer and feedback digital-to-analog converter (DAC) for a universal mobile telecommunication system (UMTS) receiver chain is presented. It achieves a dynamic range of 70 dB in a 2-MHz bandwidth and the total harmonic distortion is 74 dB at full-scale input. When used in an integrated receiver for UMTS, the dynamic range of the modulator substantially reduces the need for analog automatic gain control and its tolerance of large out-of-band interference also permits the use of only first-order prefiltering. An IC including an and modulator, phase-locked loop, oscillator, and bandgap dissipates 11.5 mW at 1.8 V. The active area is 0.41 mm in a 0.18m 1-poly 5-metal CMOS technology.

PowerDAC: a single-chip audio DAC with a 70%-efficient power stage in 0.5 /spl mu/m CMOS

The path from digital (audio) input to analog output power normally consists of a D/A converter, a low-pass filter and a class AB amplifier (having low overall power efficiency). Generally this is a two-chip solution with a D/A converter and an amplifier implemented in different technologies. This paper presents a single-chip digital amplifier combining bitstream D/A conversion with a power-efficient switching output stage (class D) without intermediate filtering. The circuit is implemented in 0.5 /spl mu/m standard CMOS technology.

A 4.4mW 76dB complex /spl Sigma//spl Delta/ ADC for Bluetooth receivers

A /spl Sigma//spl Delta/ ADC with a fifth-order continuous-time complex loop filter achieves 76dB of DNR in a 1MHz channel. The input impedance is less than 400/spl Omega/ and allows operation with a current-mode RF front-end. Image rejection is over 50dB, and IM3 distortion is below -82dBc. The circuit dissipates 4.4mW and is implemented in 0.18/spl mu/m CMOS.

A 2 mW 89 dB DR continuous-time /spl Sigma//spl Delta/ ADC with increased immunity to wide-band interferers

A continuous-time /spl Sigma//spl Delta/ ADC with merged channel filter and programmable-gain functionality is presented. Interferers above full-scale can be applied without jeopardizing reception of weak desired signals. The merged design occupies 0.14 mm/sup 2/ in 0.18 /spl mu/m CMOS, consumes 2 mW, and achieves 89 dB of dynamic range (DR) in a 1 MHz bandwidth.

A 4.7mW 89.5dB DR CT complex /spl Delta//spl Sigma/ ADC with built-in LPF

A CT complex /spl Delta//spl Sigma/ ADC with built-in LPF is presented. A modified feedback topology is used to improve robustness to interferers near f/sub g//2 or f/sub s/. Adding programmable gain control, the 0.18 /spl mu/m CMOS ADC achieves 89.5dB DR in a 1MHz BW, consuming 4.7mW from a 1.8V supply.

Continuous-time Sigma-Delta Modulators for Highly Digitised Receivers

This paper presents an overview of recent developments in continuous-time sigma-delta modulator design. Traditionally, sigma-delta modulators have been used for audio applications with low bandwidth and high-resolution requirements. Nowadays, the area of sigma-delta modulation has extended and sigma-delta modulators are widely used in multi-mode communication receivers with different bandwidth and resolution specifications. Thanks to new architectures and the integration of extra functionality, the excellent power efficiency, as well as good scalability, continuous-time sigma-delta modulators are key in enabling highly digitized receivers.