R. Roovers

An interference-robust receiver for ultra-wideband radio in SiGe BiCMOS technology

A 3.1-4.8 GHz ultra-wideband (UWB) receiver front-end for high data rate, short-range communication is presented. The receiver, based on the Multi Band OFDM Alliance (MBOA) standard proposal, consists of a zero-IF receive chain and an ultra-fast frequency-hopping synthesizer. The combination of high-linearity RF circuits, aggressive baseband filtering and low local oscillator spurs from the synthesizer results in an interference-robust receiver, having the ability to co-exist with systems operating in the 2.4-GHz and 5-GHz ISM bands. The packaged device shows an overall noise figure of 4.5 dB and has a measured input IP3 of -6 dBm and input IP2 of +25 dBm. Spurious tones generated by the synthesizer are below -45 dBc and -50 dBc in the 2.4-GHz and 5-GHz ISM bands, respectively. The hopping speed is well below the required 9.5 ns. The complete receive chain has been realized in a 0.25 /spl mu/m BiCMOS technology and draws 78mA from a 2.5-V supply.

A SiGe BiCMOS 1ns fast hopping frequency synthesizer for UWB radio

A fully integrated multi-tone generator based on 2 PLL and a SSB mixer in 0.25/spl mu/m SiGe BiCMOS achieves frequency hopping between 3.432, 3.960, and 4.488GHz within 1 ns. Spurious tones are below -50dBc in the 5GHz and -45dBc in the 2.4GHz ISM bands. The power dissipation is 73mW from a 2.7V supply. The close-in phase noise is below -90dBc/Hz and out-of-band phase noise is below -100dBc/Hz at 1MHz offset.

An interference robust receive chain for UWB radio in SiGe BiCMOS

A fully integrated receive chain for UWB radio in SiGe BiCMOS is presented. The packaged device includes a wideband LNA, a mixer, and an IF filter and has an overall NF of 7.5 dB. The IIP3 of -3 dBm and the accurately controlled and steep filter characteristic enables a robust coexistence with systems working in the 2.4 and 5 GHz bands.

A low power implementation for the transmit path of a UWB transceiver

A low power transmit path for a multiband OFDM UWB transceiver is presented. It features wideband elliptic baseband filters, a VGA with dynamic range of 12dB, an upconversion mixer and an RF output stage with power of -7dBm (3.2-4.8GHz band). The transmit path including frequency synthesizer is realized in 0.25/spl mu/m SiGe BiCMOS (70GHz f/sub t/) technology. Results show current consumption of 43mA (at 2.7V) for the complete transmit path.

Wide-Band A/D Conversion for Base Stations

A/D converters for multi-channel receiver base-stations is THE challenge in ADC design. Based on performance metrics and observations of state-of-the-art A/D converters, it can be concluded that the combined dynamic range and bandwidth requirements for multi-channel receivers will not be low power: these A/D converters will be hot. As ADCs for multi-channel receivers are not yet available, wide-band A/D converters can be used in combination with DVGA to build IF-to-digital conversion for single-channel receivers.

A fully integrated 3-band OFDM UWB transceiver in 0.25/spl mu/m SiGe BiCMOS

A fully integrated transceiver for 3-band OFDM UWB is presented. It has been implemented in a 0.25mum SiGe BiCMOS process, and has a die area of less than 4mm2. The power consumption is 47mA, 43mA, and 27mA at 2.7V supply for receiver, transmitter, and synthesizer respectively. The chip features DC offset cancellation, a loop-back test mode, a single input/output pin for antenna connection, a 1GHz baseband clock output and is robust against interferers from cellular and ISM bands. The measured EVM is 8%, while the overall NF is 4.5dB and the iIP3 is -6dBm

High Speed CMOS DA Converters for Upstream Cable Applications

In the first part of this paper the function of Analog to Digital (AD) and Digital to Analog (DA) converters in communication systems is discussed. The relation between the system data rate and the converter data rate is explored and the impact on the power dissipation in the AD and DA converter is shown. The second part describes the realisation of a DA converter for cable upstream application.

A 12 bit, 50 MSample/s Cascaded Folding & Interpolating ADC

This paper presents the analysis, design and experimental results of a 12 bits, 50 MSample/s Analog-to-Digital Converter, based on a Cascaded Folding and Interpolating architecture. The ADC is optimized for digital telecommunication applications. The integrated Track & Hold circuit enables SNR > 66 dB and THD < 72 dB, measured over an input signal bandwidth of 70 MHz. The ADC is realized in a 13 GHz, 1 μm BiCMOS process and measures 7 mm2, while dissipating 300 mW from a single 5.0 V supply.