Kathryn M. Jackson

ESA/390 interpretive-execution architecture, foundation for VM/ESA

The interpretive-execution facility of Enterprise Systems Architecture/390™ (ESA/390™) provides an instruction for the execution of virtual machines. This instruction, called START INTERPRETIVE EXECUTION (SIE), was initially created for virtualizing either System/370 or 370-XA architectures, and was used later for virtualizing ESA/370™ and ESA/390 architectures. SIE has evolved to provide capabilities for a number of specialized performance environments. Most recently it provides for the unique requirements of Enterprise Systems Architecture/Extended Configuration (ESA/XC) virtual-machine architecture. This comprehensive set of capabilities in the architecture serves as the platform for the ability of VM/ESA™ to provide functions in virtual machines for end users and system servers. This paper describes the evolution of SIE and outlines use of the various capabilities in VM/ESA.

IBM S/390 storage hierarchy: G5 and G6 performance considerations

The CMOS-based IBM S/390 Parallel Enterprise Servers™ have always employed the technique of memory caching to bridge the gap between processor speed and main-memory access time. However, that gap has widened with each succeeding system generation, requiring increasingly sophisticated, multiple-level cache structures in order to minimize memory-access latency. The IBM S/390® G5 and G6 include two-level caching, with a binodal second-level cache. This paper reviews the principles of cache design, discusses the performance requirements of S/390 relative to caching, and describes how those requirements are addressed by the binodal L2 cache in the G5 and G6 systems.

IBM system z10 performance improvements with software and hardware synergy

This paper describes efforts to more fully exploit the synergy potential between hardware and software to improve performance on the IBM System z® platform. Although the IBM commitment to upward compatibility for System z mainframes prevents us from engaging in hardware generational tuning, software stack improvements aimed at one generation of hardware tend to increase in value for subsequent generations. This paper presents some of the software synergy efforts that were made to complement hardware design characteristics to improve performance and that will continue to be of benefit in future machine generations. Also presented is IBM z/OS® HiperDispatch management, which minimizes cache coherency penalties when dispatching work, and the new IBM System z10™ hardware instrumentation, the central processor measurement facility (CPMF), which supports software performance optimizations by providing counters and sampling and allowing the software to measure central processor activities to determine hotspots. The CPMF is nondisruptive, has low overhead, and can run in multiple logical partitions simultaneously.

Storage hierarchy to support a 600 MHz G5 S/390 microprocessor

Although a microprocessors maximum frequency and internal design are important, the storage hierarchy is the primary reason for the large system performance improvement of the S/390 G5 compared to the G4. The improvement is achieved with an L2 cache, system controller and memory interface clocked at 1/4 the microprocessor frequency.