Charles F. Webb

IBM's S/390 G5 microprocessor design

The IBM S/390 G5 microprocessor in IBMs newest CMOS mainframe system provides more than twice the performance of the previous generation, the G4. The G5 system offers improved reliability and availability, along with new architectural features such as support for IEEE floating-point arithmetic and a redesigned L2 cache and processor interconnect. The G5 system implements the ESA/390 instruction-set architecture, which is based on and compatible with the original S/360 architecture. Therefore, it has no RISC (reduced-instruction-set computing) concepts and is one of the most complex of all CISC (complex-instruction-set computing) architectures. Designers had to meet a unique set of challenges to achieve the G5s level of performance-for example, achieving a very high frequency given the complexity of the architecture.

IBM z10: The Next-Generation Mainframe Microprocessor

The IBM system z10 includes four microprocessor cores - each with a private 3-Mbyte cache - and integrated accelerators for decimal floating-point computation, cryptography, and data compression. A separate SMP hub chip provides a shared third-level cache and interconnect fabric for multiprocessor scaling. This article focuses on the high-frequency design techniques used to achieve a 4.4-GHz system, and on the pipeline design that optimizes z10s CPU performance.

A 400 MHz S/390 microprocessor

A microprocessor implementing IBM S/390 architecture operates in a system at up to 400 MHz (2.5 ns). The microprocessor, initially in IBM CMOS5X technology, migrated to CMOS6S by shrinking the FET length dimensions but not shrinking the interconnect dimensions. The chip is 17.35/spl times/17.30 mm/sup 2/ with about 7.8M transistors. The power supply is 2.5 V and measured power dissipation at 300 MHz is 37 W. The microprocessor features two instruction units, two fixed point units, two floating point units, a buffer control element, and a register unit. It dispatches one instruction per cycle. A PLL provides a processor clock at 2/spl times/ the system bus frequency.

Development and attributes of z/Architecture

The IBM z/Architecture™ instruction set architecture (ISA) is an extension of the IBM Enterprise Systems Architecture/390® (ESA/390) ISA and features 64-bit general registers, 64-bit operations, and 64-bit virtual and real addressing. In addition, z/Architecture includes new instructions to optimize the handling of modern multi-byte character encodings and to improve the performance of programs written in high-level languages. It provides compatibility for ESA/390 application programs and increases the ease of development of new application programs. This paper presents an overview of the interesting aspects of z/Architecture and some of the associated decisions and tradeoffs made in its development.

A 5.2GHz microprocessor chip for the IBM zEnterprise™ system

The microprocessor chip for the IBM zEnterprise 196 (z 196) system is a high-frequency, high-performance design that adds support for out-of-order instruction execution and increases operating frequency by almost 20% compared to the previous 65nm design, while still fitting within the same power envelope. Despite the many difficult engineering hurdles to be overcome, the design team was able to achieve a product frequency of 5.2GHz, providing a significant performance boost for the new system.

Circuit and Physical Design of the zEnterprise™ EC12 Microprocessor Chips and Multi-Chip Module

This work describes the circuit and physical design implementation of the processor chip (CP), level-4 cache chip (SC), and the multi-chip module at the heart of the EC12 system. The chips were implemented in IBMs high-performance 32nm high-k/metal-gate SOI technology. The CP chip contains 6 super-scalar, out-of-order processor cores, running at 5.5 GHz, while the SC chip contains 192 MB of eDRAM cache. Six CP chips and two SC chips are mounted on a high-performance glass-ceramic substrate, which provides high-bandwidth, low-latency interconnections. Various aspects of the design are explored in detail, with most of the focus on the CP chip, including the circuit design implementation, clocking, thermal modeling, reliability, frequency tuning, and comparison to the previous design in 45nm technology.

609 MHz G5 S/399 microprocessor

The IBM G5 system is a fifth-generation CMOS server for the S/390 line of products with functionality improvements such as an instruction branch target buffer (BTB) and an IEEE compliant binary floating-point. The microprocessor operates at 600 MHz at the fast end of the process distribution, although the system is shipped at 500 MHz in a 10+2 SMP configuration. Measured system performance on the 10 way is 1069 S/390 MIPs. This microprocessor uses a 0.25 mum CMOS process. The chip uses 6 levels of metal plus an additional layer of local interconnect and is 14.6times14.7 mm2 with 25 M transistors (7 M logic/18 M array). Power supply is 1.9 V. Chip power is 25 W at 500 MHz

5.5GHz system z microprocessor and multi-chip module

The new System z microprocessor chip (“CP chip”) features a high-frequency processor core running at 5.5GHz in a 32nm high-κ CMOS technology [1], using 15 levels of metal. This chip is a successor to the 45nm product [2], with significant improvements made to the core and nest (i.e. the logic external to the cores) in order to increase the performance and throughput of the design. Also, special considerations were necessary to ensure robust circuit operation in the high-κ technology used for implementation. As seen in the die photo, the chip contains 6 processor cores (compared to 4 cores in the 45nm version), and a large shared 48MB DRAM L3 cache. Each core includes a pair of data and instruction L2 SRAM caches of 1MB each. In addition, the chip contains a memory control unit (MCU), an I/O bus controller (GX), and two sets of interfaces to the L4 cache chips (also in 32nm technology). The CP chip occupies 598 mm2, contains about 2.75B transistors, and has 1071 signal IOs.

IBM z6 - the next-generation mainframe microprocessor

This article consists of a collection of slides from the authors conference presentation on IBMs z6, the next generation mainframe family of microprocessor products. Some of the specific topics discussed include: the special features, system specifications, and system design for these products; system architectures; applications for use; platforms supported; processing capabilities; memory capabilities; and targeted markets.

A high-frequency custom CMOS S/390 microprocessor

The S/390 G4 CMOS processor is an implementation of the IBM ESA/390 architecture on a single custom CMOS chip. It is a new design which uses a straightforward pipeline both to achieve a fast cycle time and to speed the design cycle. The complex instructions are implemented using a highly privileged subroutines called millicode. To achieve high data integrity while maintaining a high clock frequency, the chip contains duplicate I- and E-units which perform the same operations each cycle and have their results compared.