Katsuhiko Degawa

A single-electron-transistor logic gate family and its application - Part I: basic components for binary, multiple-valued and mixed-mode logic

This paper presents a model-based study of an SET (single-electron-transistor) logic gate family for synthesizing binary and MV (multiple-valued) logic circuits. The use of SETs combined with MOS transistors allows a compact realization of basic logic functions that exhibit periodic transfer characteristics. These basic SET logic gates are useful for implementing binary logic circuits, MV logic circuits and binary-MV-mixed logic circuits in a highly flexible manner. As an example, this paper describes the design of various parallel counters for carry-propagation-free arithmetic, where MV signals are effectively used to achieve higher functionality with lower hardware complexity.

A two-bit-per-cell content-addressable memory using single-electron transistors

This paper presents a circuit design of a two-bit-per-cell content-addressable memory (CAM) using single-electron transistors (SETs). The key ideas of the proposed CAM architecture are (i) four-level data storage function implementing by a SET-based static memory cell and (ii) four-level data matching function employing periodic drain-current characteristics of SETs with dynamic phase-shift control. A simple multi-gate SET can be used to realize four-level data matching within a compact CAM cell circuit. As a result, the proposed two-bit-per-cell CAM architecture reduces the number of transistors to 1/3 compared with the conventional CAM architecture.

A field-programmable digital filter chip using multiple-valued current-mode logic

This paper presents a Field-Programmable Digital Filter (FPDF) IC that employs carry-propagation-free redundant arithmetic algorithms for faster computation and multiple-valued current-mode circuit technology for high-density low-power implementation. The prototype FPDF fabrication with 0.6 /spl mu/m CMOS technology demonstrates that the chip area and power consumption can be reduced to 41% and 74%, respectively, compared with the standard binary logic implementation.

Algorithm-Level Optimization of Multiple-Valued Arithmetic Circuits Using Counter Tree Diagrams

This paper presents a novel approach to designing multiple-valued arithmetic circuits based on a unified representation of addition algorithms called Counter Tree Diagrams (CTDs). By using CTDs, we can derive possible variations of addition algorithms in a systematic way without using specific knowledge about underlying arithmetic fundamentals. For any weighted number system, we can design the optimal adder structure by trying every possible CTD representation. In this paper, the potential of the CTD- based method is demonstrated through an experimental design of the Redundant-Binary (RB) adder in multiple-valued current-mode logic. We successfully obtained the RB adder that achieves about 32-57% higher performance in terms of power-delay product compared with the conventional designs.

A High-Density Ternary Content-Addressable Memory Using Single-Electron Transistors

This paper presents a circuit design of a Ternary Content-Addressable Memory (TCAM) using Single- Electron Transistors (SETs). The proposed TCAM cell employs a SET-based ternary memory and a dual-gate SET for ternary data matching. The multi-level functionality of SET is fully utilized to reduce circuit complexity. Basic matching operation of the TCAM cell is verified using a multi-gate SET and a MOSFET fabricated on the same Silicon-On-Insulator (SOI) wafer by Pattern-Dependent OXidation (PADOX) process.

Application of a continuous-time level crossing quantization method for timing noise measurements

This paper introduces a new Level-Crossing ADC (LCADC) architecture which employs the novel use of a clocked comparator. The proposed LCADC can measure a timing noise spectrum with wide dynamic range and wide frequency range. An extension of the underlying theory of the performance measurement of an LCADC is also included.

An equivalent-time and clocked approach for continuous-time quantization

This paper presents an improved design for a Level-Crossing ADC (LCADC) that incorporates both an equivalent-time method and a clocked comparator. The LCADC is experimentally validated using a 65 nm clocked comparator.

A new method for measuring alias-free aperture jitter in an ADC output

This paper proposes a new method for directly measuring alias-free aperture jitter in an ADC output. Both the average ENOB and the worst-case ENOB due to aperture jitter are also measured after the elimination of the aliasing noise. Because it adds only a negligible computation time to an existing ENOB test of a single frequency, it can also be used in an HV production environment and should reduce the overall test time by at least three times.

Phase-based alignment of two signals having partially overlapped spectra

This paper proposes a novel method for aligning two signals using the information contained in the overlapped band. In particular the proposed method aligns two signals by compensating both time-delay and phase-offset in the second signal using the estimated gradient of phase difference in the overlapped band. Compared with other conventional methods, this method can align two signals without requiring a pilot tone or additional hardware. The proposed method was experimentally validated using RF pulses.

Common pitfalls in application of a threshold detection comparator to a continuous-time level crossing quantization

Propagation delay variation of the threshold detection comparator in current-day level-crossing ADCs is a fundamental impediment to their performance. This paper reviews why commonly used threshold detection comparators can be inappropriate to detect level crossing times of high-frequency signals. The analysis presented in this paper helps establish a new common ground for developing a high-performance LCADC.