Hiroshi Inokawa

A multiple-valued logic and memory with combined single-electron and metal-oxide-semiconductor transistors

Devices that combine single-electron and metal-oxide-semiconductor (MOS) transistors are newly proposed as basic components of multiple-valued (MV) logic, such as a universal literal gate and a quantizer. We verified their operation using single-electron and MOS transistors fabricated on the same wafer by pattern-dependent oxidation of silicon. We also discuss their application to an analog-to-digital converter, a MV adder, and MV static random-access memory.

A compact analytical model for asymmetric single-electron tunneling transistors

Analytical model for asymmetric single-electron tunneling transistors (SETTs), in which resistance and capacitance parameters of source/drain junctions are not equal, has been developed. The model is based on the steady-state master equation, takes only the two most-probable charging states into account, and is therefore very simple. Even so, it can accurately reproduce the peculiar behaviors of an asymmetric SETT, such as the skew in the drain current-gate voltage characteristics and the Coulomb staircase in the drain current-drain voltage characteristic. Analytical expressions for the charge in the Coulomb island and the capacitance components of the SETT are also derived according to the same scheme, and it is demonstrated that the model can precisely describe the various aspects of the SETT behavior.

A multiple-valued logic with merged single-electron and MOS transistors

Proposes merged single-electron and MOS devices that serve as basic components of multiple-valued logic, such as a universal literal gate and a quantizer. We verified their operation by using single-electron transistors and MOSFETs fabricated on the same wafer by pattern-dependent oxidation process. We also discuss their application to an analog-to-digital converter and a multiple-valued adder.

Binary adders of multigate single-electron transistors: specific design using pass-transistor logic

We describe how to construct area-efficient adders using single-electron transistors (SETs). The design is based on pass-transistor logic and multigate SETs are used as pass transistors. The proposed design enables us to construct a full adder using only six SETs. We also show that multibit binary adders can be built using cascaded SET structures without any long wires. The small number of transistors and no-metal-interconnection configuration significantly reduces the circuit area and capacitance to be charged. A Monte Carlo simulation shows that even when the inter-SET-node capacitances are reduced and consequently the carry signal level terribly fluctuates in its path due to single-electron charging effects, the carry can correctly propagate as long as the final output node capacitance is sufficiently large. This proves that the area reduction and speed improvement are compatible in our design. We also discuss the possibility of large-scale integration, touching on the random-offset-charge issue.

Experimental and simulation studies of single-electron-transistor-based multiple-valued logic

Periodic drain current-gate voltage characteristics of single-electron transistors (SETs) were utilized to construct basic components of multiple-valued logic (MVL), such as a universal literal gate and a quantizer. In order to supplement the small gain and the small applicable voltage of the SET, hybrid SET-MOSFET scheme is proposed and demonstrated experimentally using CMOS-compatible pattern-dependent oxidation (PADOX) technology. We also succeeded in reproducing the results using a SPICE circuit simulator with a compact analytical SET model, and estimated the performance of the proposed MVL.

A single-electron-transistor logic gate family and its application - Part II: design and simulation of a 7-3 parallel counter with linear summation and multiple-valued latch functions

Guidelines for designing multi-input multi-output counters, based on a single-electron transistor (SET) logic gate family, are presented. A counter consisting of an inverting adder, latched multiple-valued (MV) quantizer, and periodic literals can be made extremely compact owing to the high functionality of SETs and a specific design that utilizes limited kinds of transistors and does not require SETs with control gates or devices for level shifting. Circuit simulation, using a physics-based SET model, reveals that the counter operates at a moderately high speed and with ultra-low power consumption.

Room-temperature single-electron transfer and detection with silicon nanodevices

Transfer and subsequent detection of single electrons are demonstrated at room temperature using a silicon-on-insulator nanodevice. The turnstile, which is composed of two Si-wire-FETs with a fine gate, enables us to transfer single electrons by opening and closing the two FETs alternately. The transferred individual electrons are stored in a single-electron box and detected by the electrometer with single-electron resolution. The present device achieves high-speed transfer and long retention.

A multiple-valued SRAM with combined single-electron and MOS transistors

Reports a new type of single-electron memory that works as a multiple-valued SRAM. A schematic of the proposed memory is shown. The source of a MOSFET with fixed gate bias V/sub gg/ is connected to the drain of a single-electron transistor (SET), and the SET drain voltage is kept nearly constant around V/sub gg/-V/sub th/, where V/sub th/ is the threshold voltage of the MOSFET. This V/sub gg/-V/sub th/ is set low enough to sustain the Coulomb-blockade condition. By connecting the SET gate to the MOSFET drain, the I/sub d/-V/sub gs/, (3-terminal) characteristics of the SET are converted to the I-V (2-terminal) characteristics of the combined SET-MOSFET circuit. With a proper choice of load device, the periodic nature of the I-V characteristics results in a number of stability points, and this realizes the multiple-valued memory operation.

Automatic control of oscillation phase of a single-electron transistor

Automatic phase control of the Coulomb-blockade (CB) oscillation of a single-electron transistor (SET) is proposed and experimentally demonstrated. Charges in the memory node (MN) capacitively coupled to the SET control the phase of the CB oscillation. The output signal of the SET can controls chares in the MN. This feedback mechanism automatically adjusts the amount of charges, so that the output signal is leveled with a requested one for arbitrary input signal of the SET. The electrical phase control realizes the demonstration of a multifunctional Boolean logic.

A multiple-valued single-electron SRAM by the PADOX process

Multiple-valued static memory consisting of a single-electron transistor (SET) and a MOSFET is proposed. The memory operation is verified by using transistors fabricated by the CMOS-compatible pattern-dependent oxidation (PADOX) process. The results indicate that a dramatic increase of CMOS memory density can be attained by the use of a SET with multiple-valued capability.