Katsuhiko Nishiwaki

Development trends of power semiconductors for hybrid vehicles

In the environmentally-friendly vehicles that are powered by electric motors, as represented by hybrid vehicles (HVs), enhancing the performance and reducing the size of the power semiconductors are becoming essential for vehicles to achieve low-fuel consumption and high-power performance. This is also the case for HV systems to facilitate adoption in multiple vehicle models. This paper looks back on the development of these power semiconductors up to the present in response to the advancement of HVs. It also surveys the future trends in power semiconductor development toward achieving the ultimate-eco vehicle.

A fast and soft recovery diode with ultra small Qrr (USQ-Diode) using local lifetime control by He ion irradiation

This paper presents an ultra small reverse recovery charge Qrr diode (USQ-Diode) for Insulated Gate Bipolar Transistor (IGBT) modules. The USQ-Diode has a thin p-layer anode with low impurity concentrations, p+ stripe anodes, and lifetime control by He ion irradiation. By employing the thin p-layer anode, the injection of holes into the n-layer as minority carriers was significantly reduced near the pn junction. By using the He ion irradiation, crystal defects for lifetime control were localized near the pn junction. With the combined effects from both the reduced injection of holes and the local lifetime control by the He ion irradiation, as compared to the conventional pn diode, the USQ-Diode realized such superior characteristics as 1/5 times smaller reverse recovery charge and 0.2 V lower forward voltage drop.

Analysis of Dynamic Avalanche Phenomenon of PiN Diode Using He Ion Irradiation

The purpose of this paper is to analyze the dynamic avalanche phenomenon of conventional PiN diodes using He ion irradiation. In conventional PiN diodes, the avalanche occurs during reverse recovery operation under high voltage and low temperature conditions, resulting in two peaks and high frequency oscillation in the recovery current. The two peaks in the current were reproduced by a simulation that introduces hole trap levels. It was also confirmed that the phenomenon can be suppressed by lowering the density of the trap levels or the minority carrier lifetime of the bulk wafer

A study of correlation between CiOi defects and dynamic avalanche phenomenon of PiN diode using He ion irradiation

Our previous research has shown that dynamic avalanche phenomenon is related to the hole trap level that is induced at an energy level of Ev+0.35 eV. In this study we will describe how we used the DLTS (deep level transient spectroscopy) method and CL (cathode luminescence) method to identify that the defects which form the hole trap level are in fact CiOi that is present in the Si wafer. We fabricated diodes using wafers with different amounts of CiOi, and conducted tests for the occurrence of the dynamic avalanche phenomenon. The results verified that the dynamic avalanche phenomenon occurs in diodes with large amounts of CiOi. By controlling the impurities in the Si wafer, we were able to improve the diode characteristics and suppress oscillation of the IGBT module current and voltage waveforms, reducing switching loss.

Investigation of Dynamic Avalanche in the Termination Region for FWDs with High Reverse Recovery Capability

This study investigated the destruction of FWDs in the termination region during reverse recovery, with the aim of enabling the fabrication of FWDs with a high current density and high reverse recovery capability. An investigation carried out by device simulation clarified that a high hole current in the termination region during reverse recovery leads to a dynamic avalanche, which may result in the destruction of the FWD. This study also demonstrated that FWDs fabricated using two concepts based on this understanding have a high current density and high reverse recovery capability without sacrificing basic characteristics.

A PT-IGBT with a p-/n+ buffer layer

A novel punch-through insulated gate bipolar transistor with a p-/n+ buffer layer was proposed to improve the characteristics of conventional high power IGBT used in motor control inverters at high voltages operation. The new structure with p-floating layer inserted between n- epi and n+ buffer layer shows higher breakdown voltage than that of conventional IGBT structures. We also demonstrate, for the first time, the performance of 900V-200A class IGBTs using this p- floating/n+ buffer structure. As a result of the measurements, the IGBT proposed here shows an on-state voltage of 1.9V at 250A/cm/sup 2/ and the fall time of 350 nsec.