Toyokazu Ohnishi

Neutron induced single-event burnout of IGBT

Cosmic-ray neutrons can trigger a single-event burnout (SEB), which is a catastrophic failure mode in power semiconductor devices. It was found experimentally that the incident neutron induced SEB failure rate increases as a function of the applied collector voltage in an insulated gate bipolar transistor (IGBT). Moreover, the failure rate increased sharply with an increase in the applied collector voltage when the voltage exceeded a certain threshold value. Transient device simulation showed that the onset of impact ionization at the n− drift/n+ buffer junction (nn+ junction) can trigger turning-on of the inherent parasitic thyristor, and then SEB subsequently occurs. In addition, it was analytically derived that reducing the current gain of the parasitic transistor was effective in increasing the SEB threshold voltage. Furthermore, ‘white’ neutron-irradiation experiments demonstrated that suppressing the inherent parasitic thyristor action leads to an improvement of the SEB threshold voltage.

Reverse Electrical Characteristics of 4H-SiC JBS Diodes Fabricated on In-House Substrate with Low Threading Dislocation Density

The impacts of threading dislocations, surface defects, donor concentration, and schottky Schottky barrier height on the reverse IV characteristic of silicon carbide (SiC) junction barrier schottky Schottky (JBS) diodes were investigated. The 100 A JBS diodes were fabricated on 4H-SiC 3-inch N-type wafers with two types of threading dislocation density. The typical densities are were 0.2×104 and 3.8×104 cm-2, respectively. The improvement of vIt was found that variations in the leakage current and the high yield of large area JBS diodes werecould be were obtained improved by using a wafer with a low threading dislocation density. In the range of low leakage current, the investigation shows showed a correlation between leakage current and threading dislocation density.

A PT-IGBT with a p-/n+ buffer layer

A novel punch-through insulated gate bipolar transistor with a p-/n+ buffer layer was proposed to improve the characteristics of conventional high power IGBT used in motor control inverters at high voltages operation. The new structure with p-floating layer inserted between n- epi and n+ buffer layer shows higher breakdown voltage than that of conventional IGBT structures. We also demonstrate, for the first time, the performance of 900V-200A class IGBTs using this p- floating/n+ buffer structure. As a result of the measurements, the IGBT proposed here shows an on-state voltage of 1.9V at 250A/cm/sup 2/ and the fall time of 350 nsec.