Katsuhiro Harada

Integrated electrical vernier to measure registration accuracy

A new high-speed integrated electrical test structure is developed to measure registration accuracy between a conductive layer and a insulating layer in a single chip. This structure utilizes a pair of digitally readable tapered comb (TC) patterns as a vernier. This eliminates measurement errors due to process variations such as resist pattern fluctuation or overetching. By incorporating transfer gate arrays and a shift register to sequentially address a desired position, a measurement speed of 500 µs/point is achieved.

A novel high‐speed nanometric electron beam lithography system: EB–F

An advanced nanometric electron beam lithography system EB–F has been developed for high‐speed writing applications beyond the laboratory. The EB–F achieves a minimum beam diameter of 30 nm with a beam current of 3 nA, a deflection field of 2×2 mm. A triple deflection system was developed to achieve the stepping rate of 100 MHz. This system consists of a magnetic main deflector, an electrostatic subdeflector and an electrostatic fill‐in deflector. The maximum size of the fill‐in field is 2×2 μm, with a minimum positioning step of 10 nm. An electron gun using a new Ti–W thermal field emitter was also adopted. The gun has high brightness of 108 A/cm2/sr and long term stability. The EB–F has two writing modes. They are the high resolution mode with 30 nm at 3 nA and the fast writing mode with 90 nm at 27 nA. They are selected by switching condenser lenses. Acceleration voltages of 20 and 50 kV can also be selected. These new technologies achieve a greater than hundredfold increase in writing speed. A chip co...

Superficial image emphasis lithography

A new approach to electron beam lithography for device fabrications is described. This technique transfers relief images formed at the superficial layer of a positive resist inversely to the bottom layer of the resist. The technique can drastically improve the resolution and linewidth accuracy of delineated patterns by reducing proximity effects and the influence of incident beam spread. Writing time can also be reduced. 0.2‐μm very large scale integration patterns and feature with 250‐A linewidth less than the incident beam size have been successfully produced.

A large angle electrostatic deflection, variable shaped, electron beam exposure system

In electron beam direct writing, a capability of ‘‘one chip within one deflection field’’ can reduce time wasted in stage moving, and eliminate field stitching errors in a chip. These advantages lead to high throughput and high overlay accuracy for successful VLSI fabrications. A large angle electrostatic deflection, variable shaped, electron beam exposure system (EB57) has been developed to achieve this capability. The key EB57 technologies are a large angle electrostatic deflection and high speed deflection control. Newly developed multiple electrostatic deflectors were designed using an in‐lens, dual channel deflection method. In this method, two types of field and subfield deflectors are equipped inside a projection lens. Deflectors free of third and fifth θ components can provide a large angle of deflection with a 10 mm2 field. 18‐bit digital‐to‐analog converters, and ±800 V amplifiers effect this large field deflection. The high breakdown voltage for the amplifiers is attained by connecting vertical...