Katsuhito Sakurai

A 1/2.7-in 2.96 MPixel CMOS Image Sensor With Double CDS Architecture for Full High-Definition Camcorders

A 1/2.7-in 1944 times 1484 pixel CMOS image sensor with double CDS architecture fabricated in a 0.18-mum single-poly triple-metal (1P3M) CMOS process is described. It operates at 48 MHz in a progressive scanning mode at 60 frames/s for full high-definition (HD) imaging. Two transistors/pixel architecture and low optical stack with double microlenses achieve 14.6 ke macr/1times ldr s sensitivity and 14 ke macr saturation. Double CDS architecture with a high-gain column amplifier realized a low noise floor of 3.5 e macrrms. Optimized shallow-trench isolation achieved very low dark current of 12.2 e macr/s (60degC). This image sensor also realizes low power consumption of 220 mW.

6.4 An APS-H-Size 250Mpixel CMOS image sensor using column single-slope ADCs with dual-gain amplifiers

Recently, there has been strong demand for high-resolution CMOS image sensors (large number of pixels) in the fields of security, science, and other specialized areas [1,2]. One of the major issues in realizing high-resolution image sensors is to speed up signal readout. For high-speed signal readout, it is necessary to accelerate pixel readout, AD conversion in column circuits, horizontal data output from column memories, and digital data output from the chip. Single-slope ADCs (SS-ADC) are the most common architecture in commercialized CMOS image sensors; increasing their counting clock frequency up to 2.376GHz [3] and using multiple ramp signals [4] can shorten the AD conversion period. However, the former has difficulty in maintaining the clock quality and suppressing power dissipation due to the high clock frequency, and the latter has difficulty in controlling the uniformity and the quality of the multiple ramp signals. Another significant issue is power consumption. Rise of power consumption with increase in number of columns results in non-uniformity of power supply to the column circuits due to IR drops. It may give rise to degradation of image quality such as fixed pattern noise, etc.

4.5 A 1.8e rms − temporal noise over 110dB dynamic range 3.4µm pixel pitch global shutter CMOS image sensor with dual-gain amplifiers, SS-ADC and multiple-accumulation shutter

CMOS image sensors (CIS) with global shutter (GS) function are required in a variety of areas, including broadcasting, automobile, drones, and surveillance applications. For these applications, GS CISs are needed to avoid rolling shutter (RS) distortion. These applications also benefit from the high image quality and high frame rates of GS CISs [1–3]. To realize a GS CIS, a memory structure and additional MOS transistors are necessary. Due to this increase in the number of components, photodiode area is restricted. Therefore, sensor performance (e.g., noise, sensitivity, and saturation) of GS CISs has generally remained inferior to that of RS sensors. To break down this constraint, we introduce a multiple-accumulation shutter technique for GS CISs. Furthermore, we combine the column single-slope ADCs with dual-gain amplifiers (SSDG-ADC) [4] to implement this technique effectively, while also achieving low power consumption and a high frame rate.