Shigetoshi Sugawa

A linear response single exposure CMOS image sensor with 0.5e − readout noise and 76ke − full well capacity

A linear response single exposure CMOS image sensor approaching to the photon countable sensitivity and a high full well capacity (FWC) is developed using lateral overflow integration capacitor (LOFIC) architecture with dual gain column amplifiers, small floating diffusion (FD) capacitance (C_FD) and low noise in-pixel source follower (SF) signal readout technologies. The fabricated 5.5 μm pitch 360^H×1680^V pixel prototype image sensor exhibited 240 μV/e^- conversion gain (CG) with 76 ke^- FWC resulting in 0.5 e^-_rms readout noise and 104 dB dynamic range under room temperature operation.

Analyzing correlation between multiple traps in RTN characteristics

The correlation between multiple traps in Random Telegraph Noise (RTN) were evaluated by using Time-Lag-Plot (TLP). The correlations between multiple traps were evaluated by transition paths on the TLP and there are two types of RTN. In the 1st case, multiple traps are independent from each other and in the second case the multiple traps have the correlation. We proposed the models for three states RTN to understanding the mechanism of them. These methods help us to understand the RTN mechanism and the correlation between multiple traps.

Atomically flattening of Si surface of silicon on insulator and isolation-patterned wafers

By introducing high-purity and low-temperature Ar annealing at 850 °C, atomically flat Si surfaces of silicon-on-insulator (SOI) and shallow-trench-isolation (STI)-patterned wafers were obtained. In the case of the STI-patterned wafer, this low-temperature annealing and subsequent radical oxidation to form a gate oxide film were introduced into the complementary metal oxide semiconductor (CMOS) process with 0.22 µm technology. As a result, a test array circuit for evaluating the electrical characteristics of a very large number (>260,000) of metal oxide semiconductor field effect transistors (MOSFETs) having an atomically flat gate insulator/Si interface was successfully fabricated on a 200-mm-diameter wafer. By evaluating 262,144 nMOSFETs, it was found that not only the gate oxide reliability was improved, but also the noise amplitude of the gate–source voltage related to the random telegraph noise (RTN) was reduced owing to the introduction of the atomically flat gate insulator/Si interface.

Random telegraph noise measurement and analysis based on arrayed test circuit toward high S/N CMOS image sensors

Using the developed array test circuit, both static and temporal electrical characteristics of over million transistors/shot were measured with the accuracy of 60 μVrms to analyze and reduce random telegraph noise (RTN) toward high S/N CMOS image sensors. Statistical evaluation results of RTN parameters such as time constants and amplitude and their behaviors toward transistor device structures and operation conditions are summarized. Application to high S/N CMOS image sensor is also described.

Demonstrating distribution of SILC values at individual leakage spots

Stress induced leakage current (SILC) in the order of 10-17 to 10-13 A were statistically evaluated by using an advanced test circuit. In this paper, the distribution of SILC was evaluated by changing measurement electric fields, electric stress intensities, device area, and oxide thickness. The distribution of SILC is determined by the current values at individual leakage spots when the device area is sufficiently small. When the electric stress intensity and the measurement field are small, the distribution of logarithm of SILC follows the Gumbel distribution because the maximum current values of the leakage spots determine the gate leakage current in small area MOSFETs. We also evaluated the time-dependent characteristics of SILC in small area MOSFETs. The random telegraph signals of gate leakage current were observed which also indicates the current values of individual leakage spots.

A novel analysis of oxide breakdown based on dynamic observation using ultra-high speed video capturing up to 10,000,000 frames per second

Dynamic visualization results of 100 nm-thick oxide breakdown are demonstrated in this work realized by the ultra-high speed video capturing with a frame rate of up to 10M frame-per-second. The correlation of the time-dependent-dielectric-breakdown failure mode and light emission mode are confirmed.

High-speed and highly accurate evaluation of electrical characteristics in MOSFETs

Threshold voltage variability, random telegraph signal, and leakage current of gate oxides and pn junctions of numerous MOSFETs are evaluated by the array test circuits. By converting from current signal of MOSFETs to the voltage signal in the test circuit, accurate and high speed measurement can be obtained. These numerous data of variability, noise, and leakage current caused by the defects in MOSFETs are very useful for the process development and constructing the device structures.

Analysis of pixel gain and linearity of CMOS image sensor using floating capacitor load readout operation

In this paper, we demonstrate that the floating capacitor load readout operation has higher readout gain and wider linearity range than conventional pixel readout operation, and report the reason. The pixel signal readout gain is determined by the transconductance, the backgate transconductance and the output resistance of the in-pixel driver transistor and the load resistance. In floating capacitor load readout operation, since there is no current source and the load is the sample/hold capacitor only, the load resistance approaches infinity. Therefore readout gain is larger than that of conventional readout operation. And in floating capacitor load readout operation, there is no current source and the amount of voltage drop is smaller than that of conventional readout operation. Therefore the linearity range is enlarged for both high and low voltage limits in comparison to the conventional readout operation. The effect of linearity range enlargement becomes more advantageous when decreasing the power supply voltage for the lower power consumption. To confirm these effects, we fabricated a prototype chip using 0.18um 1-Poly 3-Metal CMOS process technology with pinned PD. As a result, we confirmed that floating capacitor load readout operation increases both readout gain and linearity range.

A Test Circuit for Statistical Evaluation of

We develop a test circuit to evaluate statistical distributions of p-n junction leakage currents for numerous samples in a very short time (0.1-10 fA, 28672 n+-p diodes in 0.77s). This test circuit is based on a complementary metal-oxide-semiconductor active pixel image sensor, which contains a current-to-voltage conversion function by a capacitor and amplifiers of voltage signals in each pixel. The test structure can be easily designed because of a small number of mask layer requirements (at least one poly-Si, one metal interconnect layer). Its simplicity has considerable benefits, such as an easy fabrication for the evaluation of various processes technologies without exceptional cares. We demonstrate that two normal distributions exist in the steady-state (time averaging) Ileak distributions, which have differing temperature dependencies. A distribution of the activation energy extracted from temperature dependence of Ileak is also revealed experimentally. Dynamic fluctuation of Ileak is confirmed to be measured, due to the execute pseudoparallel sampling among whole samples over a long recording time.

p-n

In this work, the origin of the leakage current of a highly area-efficient silicon-on-insulator (SOI) monolithic isolator using a spiral trench isolation structure is clarified by experimental and simulation analyses and its reduction method is proposed. It was found that parasitic MOSFET inversion and accumulation channels formed at the SOI and buried oxide (BOX) interface are the origins of leakage current. To reduce the leakage current, adequate SOI spiral length and width and BOX layer thickness are proposed for various voltage usages and show the possibility of 4 kV voltage tolerance and 500 MΩ isolation resistivity.