Katsunori Hirase

A reconfigurable processor based on ALU array architecture with limitation on the interconnection

Dynamic reconfigurable processor based on ALU array architecture for consumer appliances is described. To implement reconfigurable system on portable or mobile products, we have tried to develop smaller and powerful reconfigurable processor. We have proposed the ALU array architecture with the limitation on the interconnection for area reduction. By the proposed architecture, we could reduce gate size by 63% on interconnections. Also, we have shown that the performance of proposed architecture is almost the same as one without limitations. The proposed processor is a parallel processing processor that consists of a sequencer and an ALU array, adopted multi threading technology. We have developed compilation tools from source codes written in C language for the proposed processor. We demonstrate the software model of the processor using MPEG-4 video decoding application.

Reconfigurable processor based on ALU array architecture for software radio

We have developed an original reconfigurable processor LSI for software radio systems for consumer products. The die size of the LSI is 5.65 mm by 5.65 mm. The processor is based on ALU array architecture and has original limitations on connections of ALUs. The circuit size is small because of the limitations. It achieves high processing performance by processing multiple threads simultaneously. We have developed a prototype of a broadcasting receiver with the LSIs. The prototype has realised the real-time reception of three kinds of broadcasts by changing software using a maximum of two LSIs. We also have estimated a power consumption of the LSI and have confirmed that power consumption can be reduced by approximately 55% of that of the LSI. By doing so, we have advanced a realisation of software radio for consumer products.