Katsunori Nishii

New rapid thermal annealing for GaAs digital integrated circuits

A new rapid thermal annealing (RTA) method that uses GaAs guard rings has been developed. A new temperature monitoring method is also described. Generations of slip lines on 2‐in.‐diam GaAs wafers annealed in different kinds of RTA arrangements were investigated by x‐ray transmission topography. The use of three GaAs guard rings has been found to be very effective in reducing slip lines. The temperature dependence of activation and uniformity of annealing characteristics for a selective Si‐implanted 2‐in.‐diam GaAs wafer at 100 keV with a dose of 5×1012 cm−2 were evaluated by drain saturation current (Idss) distribution of gateless field‐effect transistors (FETs) over the wafer. The best uniformity, as well as the highest activation, was obtained by RTA at 920 °C for 15 s. The activation energy of 1.47 eV for the average value of Idss (∼(Idss)) was obtained. By using this RTA method, GaAs digital integrated circuits (ICs), dual‐modulus prescalers, have been successfully fabricated with high yield for the ...

Low-noise InGaAs HEMT using the new off-set recess gate process

A low-noise InGaAs HEMT (High electron mobility transistor) with a noise figure of 0.68 dB at 12 GHz has been developed using the offset recess gate process. The pseudomorphic n-AlGaAs/InGaAs HEMT structure was grown on a semi-insulating GaAs substrate by molecular-beam epitaxy. The offset recess gate process makes it possible to decrease the source and gate resistance. The breakdown voltage between gate and drain were above 6 V. A G/sub m/ of 510 mS/mm at minimum noise bias point was obtained in a 0.2- mu m-gate InGaAs HEMT. The minimum noise figure and associated gain of the device are 0.68 dB and 10.4 dB at V/sub ds/=2V, I/sub ds/=16 mA, and f=12 GHz, respectively. A three-stage amplifier using the new HEMT at the head has shown a minimum noise figure of 1.2 dB and a maximum gain of 31 dB.<<ETX>>

Novel High-Performance N-AlGaAs/InGaAs/N-AlGaAs Pseudomorphic Double-Heterojunction Modulation-Doped FETs

High-current driving pseudomorphic N-AlGaAs/InGaAs/N-AlGaAs double-heterojunction modulation-doped FETs (DH MODFETs) with high K-values have been successfully fabricated using an improved layer structure. The structure has been made by simply incorporating a thin N-AlGaAs layer at the heterointerface between the InGaAs and GaAs buffer layers of a conventional GaAs/InGaAs/N-AlGaAs pseudomorphic MODFET structure. A very high transconductance of 835 mS/mm and a K-value of 698 mA/(V2mm) were achieved at room temperature for a 0.35 µm-gate FET. Microwave results showed an fT of 64 GHz.

A highly miniaturized receiver front-end hybrid IC using on-chip high-dielectric constant capacitors for mobile communication equipment

A highly miniaturized and low power consumption receiver front-end hybrid IC(HIC) including input matching circuits for 880 MHz bands using on-chip high-dielectric constant (/spl epsi//sub r/) capacitors has been newly developed. The HIC is composed of a GaAs IC chip and a ceramic substrate with spiral inductors on its surface. The HIC showed conversion gain of 20.2 dB and noise figure of 4.2 dB at supply voltage of 2.7 V and dissipation current of 3.7 mA. The HIC measures only 5.0 mm/spl times/5.0 mm/spl times/1.0 mm.<<ETX>>

Step gain amplifier with impedance unchanged in gain control

A novel gain control method without impedance alternation in a gain control action has been developed. The method was based on the traditional current switch gain control scheme. A low gain mode has not only a DC feed-through as in the conventional method but also an RF feed-through with an RC network and a common-base transistor. An implemented differential Low Noise Amplifier exhibited the complete suppression of the impedance alternation effect. The details of the circuit topology are presented in this paper.

RF power characteristics of SiGe heterojunction bipolar transistor with high breakdown voltage structures

The collector profile dependences of RF power characteristics of SiGe HBT have been studied. A selectively ion implanted collector (SIC) structure with a thick and lightly doped collector layer showed good RF power characteristics including the adjacent-channel-power-ratio characteristics for middle class power around output power of 16 dBm while maintaining BV/sub CEO/ over 5 V. The maximum BVCEO of 9 V was obtained using the same process only by removing the SIC structure. Both structures are available to fabrication of multi-stage RF power amplifier on to one chip by single process.

Novel fabrication technique for 0.1 μm T-shaped gate with i-line negative resist and poly(methylmethacrylate)

We report on a novel fabrication technique for 0.1 μm T-shaped gates using electron beam and i-line lithography. This technique adopts a TLOR-N001 (i-line negative resist)/950k poly(methylmethacrylate) (PMMA) bilayer system. From Fourier-transform infrared spectrum analysis, we found a 70 nm mixed layer of PMMA and TLOR was formed at the interface of these resists which offers suitable overcut resist profile for the T-shaped gate but also enhances the resistance of the PMMA against dry etching. By utilizing this process, we obtained a 0.12 μm gate length T-shaped gate and applied it to the fabrication of an AlGaAs/InGaAs pseudomorphic high electron mobility transistor with a fT and fmax as high as 66 and 190 GHz.

High-Current and High-Transconductance Self-Aligned P^+-GaAs Junction HFET of Complete Enhancement-Mode Operation

High-current and high-transconductance self-aligned p+-GaAs junction HFETs (PJ-HFETs) of a complete enhancement-mode operation have been developed for the first time. Due to the advantages of the p/n junction, the barrier height of 1.12 eV has been obtained. To obtain high activation for the Si implanted epitaxial layers, we optimized the annealing conditions. The 0.8 µm-gate complete enhancement mode PJ-HFET with a large forward gate voltage swing of more than 1.5 V exhibited a K-value of 400 mS/Vmm, a maximum transconductance (gmMAX) of 410 mS/mm and a maximum drain current (IMAX) of 380 mA/mm with a threshold voltage (Vth) of 0.2 V. The standard deviation of Vth was 18.4 mV across a 3 inch wafer. Operated with a drain bias of 3.3 V, the PJ-HFET demonstrated a power-added efficiency (PAE) of 39.5% with an adjacent channel leakage ratio (ACPR) of -57.4 dBc at an output power (Pout) of 21.5 dBm and a frequency of 1.9 GHz.

A High-Transconductance AlGaAs/GaAs/AlGaAs Selectively-Doped Double-Heterojunction Fet With Pd-Buried Gate Structure

A high-transconductance AlGaAs/GaAs/AlGaAs selectively-doped double-heterojunction FET (SD-DH FET) with 1μm gate length has been fabricated by using high-quality epitaxial layer grown by MBE and Pd-buried gate structure. The double-heterojunction structure showed high sheet electron concentration of 2.5x10 12 /cm 2 and high electron mobility of 37000cm 2 /Vs at 77K. The sheet resistance at room temperature was 450 ohm/sq., which is about one half of that for a conventional high electron mobility transistor (HEMT). Systematic change of SD-DH FET characteristics with threshold voltage variation has been studied by gradually burying Pd into AlGaAs layer. It was found that transconductance of SD-DH FET monotonically increased for threshold voltage up to 0.1V, at which maximum extrinsic transconductance of 500mS/mm 7 was obtained. The estimated saturation velocity of electrons in SD-DH FET was 1.7 -2.0x10 7 cm/s, which is comparable to that of HEMT. The SD-DH FET has been shown to be superior to conventional HEMT fabricated at the same time in high current drivability, high transconductance and lower drain conductance.

Growth and properties of N-AlGaAs/InGaAs selectively-doped single- and double-heterojunction fet structures

Abstract We have systematically studied the dependence of electrical properties for strained N-AlGaAs/InGaAs selectively-doped single-heterojunction (SD-SH) and double-heterojunction (SD-DH) structures on the growth temperature and their structural parameters. It has been found that these structures show good electrical characteristics in the wide range of growth temperatures from 460 to 540°C. The critical layer thickness determined by the change of electrical properties in these systems were in good agreement with those calculated by People and Beans energy balance model. The SD-DH structures were found to offer not only higher electron concentration, but also higher electron mobility than SD-SH structures, probably due to the higher confinement efficiency of electrons in the InGaAs quantum well. An Al mole fraction in the AlGaAs barrier layers of higher than 0.2 is found to be desirable to obtain high electron mobility especially in SD-SH structures.