Mitsuru Nishitsuji

A low-impedance coplanar waveguide using an SrTiO/sub 3/ thin film for GaAs power MMIC's

A novel structure for coplanar-waveguide transmission lines with low impedance and low loss is demonstrated in this paper. The new structure simply has a high dielectric SrTiO/sub 3/ thin film underneath the coplanar conductors. Due to the high dielectric constant of SrTiO/sub 3/, the coplanar line exhibited characteristic impedance as low as 18 /spl Omega/ with a slot width of 5 /spl mu/m and the center conductor width of 50 /spl mu/m, while a conventional coplanar line on GaAs showed only 30 /spl Omega/ with the same configuration. The newly developed coplanar structure is easily applicable for present GaAs monolithic-microwave integrated-circuit (MMIC) technology, especially for power MMICs and low-impedance devices.

Substrate Potential Effects on Low-Temperature Preparation of SrTiO3 Thin Films by RF Magnetron Sputtering

SrTiO3 films have been prepared by RF magnetron sputtering at a low substrate temperature of 200?C. The dielectric properties of the films deposited wherein substrate potentials were floated were fairly dependent on the film thickness, which was related to a change of the substrate potential at the initial stage of deposition. In order to control the substrate potential, positive DC bias voltages were applied on substrates, so that leakage current densities of the films were markedly reduced while their dielectric constants and structural properties remained almost the same. A 300-nm-thick film deposited with DC bias voltages >+5 V exhibited. good dielectric properties with a leakage current density of 1?10-7 A/cm2 and a dielectric constant of 90.

A highly miniaturized receiver front-end hybrid IC using on-chip high-dielectric constant capacitors for mobile communication equipment

A highly miniaturized and low power consumption receiver front-end hybrid IC(HIC) including input matching circuits for 880 MHz bands using on-chip high-dielectric constant (/spl epsi//sub r/) capacitors has been newly developed. The HIC is composed of a GaAs IC chip and a ceramic substrate with spiral inductors on its surface. The HIC showed conversion gain of 20.2 dB and noise figure of 4.2 dB at supply voltage of 2.7 V and dissipation current of 3.7 mA. The HIC measures only 5.0 mm/spl times/5.0 mm/spl times/1.0 mm.<<ETX>>

Self-aligned emitter power HBT and self-aligned gate power HFET for low/unity supply voltage operation in PHS handsets

Abstract A new power HBT and HFET were developed for low unity supply voltage operation in PHS handsets. The emitter region, the emitter electrode, the buried collector and the base electrodes in the power HBT are formed using the emitter electrode self-alignment process in order to reduce parasitic resistance and capacitance. The wirings on each electrode of the HBT are formed by Au plating technique for high current operation. The gate electrode in the power HFET is self-aligned to the drain/source electrodes by using the drain/source contact mesas as a mask, where the distance between the drain and the source is minimized and the parasitic resistances are reduced. In addition, an asymmetrical double-doped structure of AlGaAs/GaAs/InGaAs/AlGaAs is applied to the HFET in order to obtain a high current density. Both the power HBT and HFET exhibited the knee voltage less than 1 V with the maximum current more than 500 mA. The power HBT performed a power gain of 14.2 dB, an efficiency of 33.8% and the power HFET performed 12.5 dB and 34.5%, with a sufficient margin of distortion for PHS standard at an output power of 22 dBm, a supply voltage of 3.5 V and a frequency of 1.9 GHz under the unity operation.

Rapid thermal annealing of Si‐implanted GaAs using the Ga‐doped spin‐on glass films

We have studied rapid thermal annealing (RTA) of Si‐implanted GaAs using Ga‐doped spin‐on glass (SOG) film for the first time. Three kinds of films such as Ga‐doped SOG, undoped SOG, and SiO2 formed by the chemical vapor deposition (CVD) method were compared. The annealed GaAs layers were characterized by sheet resistance, capacitance‐voltage (C‐V), deep level transient spectroscopy (DLTS), and photoluminescence (PL) measurements. The secondary ion mass spectroscopy (SIMS) measurement was also performed to investigate the atomic behavior at the insulating film/GaAs interface during annealing. Ga‐doped SOG film as an anneal cap of GaAs offers activation efficiency as compared with CVD‐SiO2 and undoped SOG film. The PL spectra for the annealed sample with Ga‐doped SOG cap exhibited the lowest intensity at 1.36 eV broad band emission, which suggests the suppression of the generation of Ga‐vacancy related acceptor level during annealing.

Difference between the Face Up and Face to Face Methods in AsH3 Capless Annealing of LEC-GaAs

In order to determine why the AsH3 capless annealing of ion implanted GaAs does not necessarily yield good reproducibility, conductive LEC-GaAs was annealed in AsH3/H2 flow with face up and face to face configurations. The surface carrier and EL2 concentrations decreased extensively when the wafer was annealed in the face up configuration, whereas they did not decrease for the face to face configuration. We found that a deep acceptor level, called HL2 or LPE-B, was introduced at the surface when the wafer was annealed in the face up configuration, even if a sufficient amount of As partial pressure was supplied. The introduction of this hole trap was more enhanced for an annealing in H2 than in Ar.

High-Current and High-Transconductance Self-Aligned P^+-GaAs Junction HFET of Complete Enhancement-Mode Operation

High-current and high-transconductance self-aligned p+-GaAs junction HFETs (PJ-HFETs) of a complete enhancement-mode operation have been developed for the first time. Due to the advantages of the p/n junction, the barrier height of 1.12 eV has been obtained. To obtain high activation for the Si implanted epitaxial layers, we optimized the annealing conditions. The 0.8 µm-gate complete enhancement mode PJ-HFET with a large forward gate voltage swing of more than 1.5 V exhibited a K-value of 400 mS/Vmm, a maximum transconductance (gmMAX) of 410 mS/mm and a maximum drain current (IMAX) of 380 mA/mm with a threshold voltage (Vth) of 0.2 V. The standard deviation of Vth was 18.4 mV across a 3 inch wafer. Operated with a drain bias of 3.3 V, the PJ-HFET demonstrated a power-added efficiency (PAE) of 39.5% with an adjacent channel leakage ratio (ACPR) of -57.4 dBc at an output power (Pout) of 21.5 dBm and a frequency of 1.9 GHz.

0.4-8 GHz broadband MMICs in novel RF chip size package for optical video distribution system

0.4-8 GHz broadband MMICs in the novel RF chip size package (RF-CSP) have been developed for the optical video distribution system. By using anisotropic conductive film (ACF) for the flip-chip bonding, fabrication process of RF-CSP becomes very simple and cost effective. This RF-CSP is one of the smallest packages ever reported.

A low-current and low-distortion wideband amplifier using 0.2-/spl mu/m gate MODFET fabricated by using phase-shift lithography

We have developed a wide-band amplifier that can keep a gain over 10 dB at an operation current of 10 mA from 100 MHz to 3 GHz. The fabricated integrated circuit (IC) achieved a high-output third-order intercept point of 30 dBm and low noise figure of 1.6 dB at 800 MHz, respectively. The present IC employs a MODFET with 0.2-/spl mu/m gate fabricated by using a phase-shift lithography technique.

Annealing Behavior of Low-Temperature-Deposited SrTiO3 Capacitor

as the ohmic alloying temperature of GaAs-FET. The E was widely distributed after the annealing, and the average capacitance was also increased. However, the er distribution was decreased by increasing the annealing time. In order to obtain the accurate capacitance, it is important to investigate this q variation phenomena. In this paper, we studied the thermal behavior of the LTD-STO capacitor, and investigated the relationship between the dierectric properties and the relaxation of the distortion in the STO film. We will be able to control this relaxation by adopting the annealing process subsequently after the STO deposition.