Katsuto Nakajima
Mitsubishi
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Publication
Featured researches published by Katsuto Nakajima.
New Generation Computing | 1990
Nobuyuki Ichiyoshi; Kazuaki Rokusawa; Katsuto Nakajima; Yu Inamura
This paper describes a new external reference management scheme for KL1, a committed choice logic programming language based on GHC. The significance of the new scheme is that it realizes incremental inter-processor garbage collection. Previous distributed implementations of committed choice languages had not seriously addressed inter-processor garbage collection.Incremental inter-precessor garbage collection is realized by the Weighted Export Counting (WEC). It is a first attempt to use the weighted reference counting technique in logic programming language implementation, and is also new in that it has introduced export and import tables for making independent local garbage collection possible and reducing the number of inter-processor read requests.The problems with exhaustion of reference counts and indirect exportation are discussed. Since the binding order rule adopted in our previous implementation for avoiding creation of reference loops is insufficient in the presence of indirect exportation, a new binding order rule is introduced. We prove that avoidance of reference loops is guaranteed and also prove that the unification procedure always terminates for non-circular structures.
international conference on computer design | 1990
Hiroshi Nakashima; Yasutaka Takeda; Katsuto Nakajima; Hideki Andou; Kiyohiro Furutani
The architecture of a pipelined microprocessor for logic programming languages is presented. The microprocessor, called PU (processing unit), is also used as a key component of AI workstations. PU has the capability to execute two different logic programming languages, KL1 for PIM/m and ESP for the AI workstation. The microprocessor has very high performance, 833 KLIPS in KL1 append and 1282 KLIPS in ESP, owing to the pipelined data typing and dereference. For efficient implementation of both languages, data typing and dereference are important. For these operations, PU has mechanisms to manipulate tagged data. The hardware architecture of PU is described, focusing on its data typing and dereference mechanisms.<<ETX>>
Archive | 1999
Hiroyoshi Asami; Hakuro Mori; Katsuto Nakajima; Hiroyuki Sato; 克人 中島; 裕幸 佐藤; 伯郎 森; 廣愛 浅見
SLP | 1987
Hiroshi Nakashima; Katsuto Nakajima
international conference on lightning protection | 1989
Katsuto Nakajima; Yu Inamura; Kazuaki Rokusawa; Nobuyuki Ichiyoshi; Takashi Chikayama
Future Generation Computer Systems | 1988
Atsuhiro Goto; Masatoshi Sato; Katsuto Nakajima; Kazuo Taki; Akira Matsumoto
Future Generation Computer Systems | 1992
Hiroshi Nakashima; Katsuto Nakajima; Seiichi Kondo; Yasutaka Takeda; Yu Inamura; Satoshi Onishi; Kanae Masuda
Archive | 2009
Katsuto Nakajima; 克人 中島
Future Generation Computer Systems | 1988
Shunichi Uchida; Kazuo Taki; Katsuto Nakajima; Atsuhiro Goto; Takashi Chikayama
international parallel and distributed processing symposium | 2002
Hideyuki Izumi; Kazushi Sasaki; Katsuto Nakajima; Hiroyuki Sato
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