Kiyohiro Furutani

A built-in Hamming code ECC circuit for DRAMs

An error checking and correcting (ECC) technique that checks multiple cell data simultaneously and allows fast column access is described. The ECC circuit is optimized with respect to the increase in the chip area and the access-time penalty, and can be applied to a 16-Mbit DRAM with 20% chip area increase and less access-time penalty. The soft error rate has been estimated to be about 100 times smaller than that of the basic horizontal-vertical parity-code ECC technique. >

An efficient back-bias generator with hybrid pumping circuit for 1.5-V DRAMs

An efficient back-bias (V/sub bb/) generator with a newly introduced hybrid pumping circuit (HPC) is described. This system attains a V/sub bb/ level of /spl minus/1.44 V at V/sub cc/=1.5 V, compared to a conventional system in which V/sub bb/ only reaches /spl minus/0.6 V. HPC can pump without the threshold voltage (V/sub th/) loss that conventional systems suffer. HPC is indispensable for 1.5-V DRAMs, because a V/sub bb/ level lower than /spl minus/1.0 V is necessary to meet the limitations of the V/sub th/, of the access transistor. HPC uses one NMOS and one PMOS pumping transistor. By adopting a triple-well structure at the pumping circuit area, the NMOS can be employed as a pumping transistor without minority carrier injection. >

An adjustable output driver with a self-recovering Vpp generator for a 4M/spl times/16 DRAM

An adjustable output driver with a self-recovering Vpp generator for a 4 M/spl times/16 DRAM (dynamic random-access memory) is presented. Its driver characteristics can easily be changed between fast mode and slow mode in the assembly process. The driver with a small inductance load operates 2.5 ns faster in fast mode than in slow mode, and the driver in slow mode reduces the initial drive current and prevents ringing waveforms even with large inductance load. With a 5 pF capacitance load and 20 cm wire, the ringing amplitude in slow mode is reduced to 1/3 that of the fast mode. Users can choose the operation mode of the output driver according to their application. The self-recovering Vpp generators feed 16 output drivers and control the generator capacity according to the data pattern to supply the same amount of Vpp charge consumed by output drivers. The Vpp generator saves 3.9 mA on average at a 25 ns read cycle.

A 4-Mbit DRAM with folded-bit-line adaptive sidewall-isolated capacitor (FASIC) cell

A 5-V 4-Mb word/spl times/1-b/1-Mb word/spl times/4-b dynamic RAM with a static column model and fast page mode has been built in a 0.8-/spl mu/m twin-tub CMOS technology with single-metal, two-polycide, and single poly-Si interconnections. It uses an innovative folded-bit-line adaptive sidewall-isolated capacitor (FASIC) cell that measures 10.9 /spl mu/m/SUP 2/ and requires only a 2-/spl mu/m trench to obtain a storage capacitor of 50 fF with 10-nm SiO/SUB 2/ equivalent dielectric film. A shared-PMOS sense-amplifier architecture used in this DRAM provides a low power consumption, small C/SUB B/-to-C/SUB S/ capacitance ratio, and accurate reference level for the nonboosted word-line scheme with little area penalty. These concepts have allowed the DRAM to be housed in the industry standard 300-mil dual-in-line package with performances of 90-ns RAS access time and 30-ns column address access time.

A skew and jitter suppressed DLL architecture for high frequency DDR SDRAMs

This paper demonstrates a skew and jitter suppressed delay locked loop (DLL) architecture used for over 400 Mbps operating DDR SDRAMs. Two novel replica adjusting techniques are introduced, which reduce timing skews between external clocks and data outputs. An improved delay line architecture is introduced, which realizes a high frequency and jitter suppressed DLL.

A mixed-mode voltage down converter with impedance adjustment circuitry for low-voltage high-frequency memories

This paper proposes a low voltage operation technique for a voltage down converter (VDC) using a mixed-mode VDC (MM-VDC), that combines an analog VDC and a digital VDC, and provides high frequency application using an impedance adjustment circuitry (IAC). The MM-VDC operates with a small response delay and a large supply current. Moreover, the IAC is adopted by the MM-VDC for wide range frequency operation under low voltage conditions. The IAC can change the supply current capability in accordance with the load operation frequency to avoid the overshoot and undershoot problems caused by the unmatched supply current. A 64 Mb-DRAM test device operated with the MM-VDC achieves well-controlled internal voltage (VCI) level and achieves high frequency operation. These systems, the MM-VDC and the IL-VDC, can be applicable for both low voltage and high frequency operation.

A speed-enhanced DRAM array architecture with embedded ECC

An array architecture with countermeasures for the smaller signal charge caused by scaling down is proposed. Based on a new access model, the combination of a hierarchical data bus configuration and multipurpose register (MPR) provides high-speed array access. The MPR also includes practical array-embedded error checking and correcting (ECC) with little area penalty and no access overhead in the page mode. The array architecture is applied to a scaled-down 16-Mb DRAM and has achieved high performance. >

An automatic temperature compensation of internal sense ground for subquarter micron DRAM's

This paper describes DRAM array driving techniques and the parameter scaling techniques for low voltage operation using the boosted sense ground (BSG) scheme and further improved methods. Temperature compensation and adjustable internal voltage levels maintain a small subthreshold leakage current for a memory cell transistor (MC-Tr), and a distributed BSG (DBSG) scheme and a column decoded sensing (CDS) scheme achieve the effective scaling. These schemes can set the DRAM array free from the leakage current problem and the influence of temperature variations. Therefore, parameters for the MC-Tr, threshold voltage (V/sub th/), and the boosted voltage for the gate bias can be scaled down, and it is possible to determine the V/sub th/ of the MC-Tr simply (0.45 V at K=0.4) for the satisfaction of the small leakage current, for high speed and stable operation, and for high reliability (V/sub PP/ is below 2 V/sub CC/). They are applicable to subquarter micron DRAMs of 256 Mb and more. >

A board level parallel test and short circuit failure repair circuit for high-density, low-power DRAMs

The authors present a board level parallel test circuit which greatly increases the throughput of test operations for high-density DRAMs. Also described is a short circuit failure repair circuit which enhances the yield of super low power DRAMs. They are both useful for the manufacturing of high-density, low-power DRAMs.

A pipelined microprocessor for logic programming languages

The architecture of a pipelined microprocessor for logic programming languages is presented. The microprocessor, called PU (processing unit), is also used as a key component of AI workstations. PU has the capability to execute two different logic programming languages, KL1 for PIM/m and ESP for the AI workstation. The microprocessor has very high performance, 833 KLIPS in KL1 append and 1282 KLIPS in ESP, owing to the pipelined data typing and dereference. For efficient implementation of both languages, data typing and dereference are important. For these operations, PU has mechanisms to manipulate tagged data. The hardware architecture of PU is described, focusing on its data typing and dereference mechanisms.<<ETX>>