Katsuyuki Ikeuchi

Startup Techniques for 95 mV Step-Up Converter by Capacitor Pass-On Scheme and

This paper presents a 95 mV startup-voltage step-up DC-DC converter for energy harvesting applications. The capacitor pass-on scheme enables operation of the system from an input voltage of 95 mV without using additional off-chip components. To compensate for the die-to-die process variation, post-fabrication threshold voltage (VTH) trimming is applied to reduce the minimum operating voltage (VDDMIN) of the oscillator. Experimental results demonstrate the 34% VDDMIN reduction of the oscillator by post-fabrication VTH trimming. The proposed step-up converter achieves the lowest startup voltage in standard CMOS without using a mechanical switch or large transformer.

{\rm V}_{\rm TH}

Harvesting energy from the environment by using a thermoelectric generator (TEG) or photovoltaic cells provides a solution for battery-free sensor networks or electronic healthcare systems. In these systems, the harvested energy is supplied at a very low voltages, requiring a low-startup-voltage power circuit for kick-start from low voltage. A previous sub-100mV-startup-voltage boost converter [1] was implemented by using a mechanically assisted step-up process that needs vibration at startup and the application is rather limited. In this paper, a 95mV startup voltage step-up converter without any mechanical stimulus extends the applicability of energy harvesting. The circuit converts a 100mV input to a 0.9V output with 72% conversion efficiency without any external clocks or mechanical switches. A capacitor pass-on scheme eliminates an additional external output capacitor that functions only at the startup.

-Tuned Oscillator With Fixed Charge Programming

Wafer-level simultaneous testing (WLST) where all chips on a wafer are tested and burned in at the same time is preferable in reducing the cost of obtaining Known Good Dies (KGDs). At present, however, it is difficult to realize the WLST because it requires a probe card with some hundred thousand needles, leading to more than a ton of force needed for stable contact of all needles. Non-contact probing has been proposed based on a chip-to-chip inductively-coupled interface [1] which can reduce the force but it needs a probing chip built specific to a certain product, which is costly. Recently, a low-cost membrane-based probing technique has been disclosed which makes use of the atmospheric pressure and 700kg of force can be uniformly distributed over a 300mm wafer [2]. Yet, since a contacting bump is used and each bump requires 4g of force, the number of pins is limited to about 150K, which is still the world biggest pin counts ever reported.

A 95mV-startup step-up converter with V th -tuned oscillator by fixed-charge programming and capacitor pass-on scheme

A high-speed, low-power capacitive-coupling transceiver is presented for wireless wafer-level testing systems. The proposed transceiver achieves the highest data rate of 15Gb/s in 65nm CMOS process which is 7.5 times higher than previous work. The parallel termination increases the signal bandwidth in a printed circuit board (PCB) by 8.5 times. The glitch signaling reduces the static power consumption of conventional nonreturn-to-zero (NRZ) signaling by 30%. These two design techniques lead to the lowest energy per bit of 0.47pJ/b in a chip-to-board communication.

Capacitively coupled non-contact probing circuits for membrane-based wafer-level simultaneous testing

A novel Switched Resonant Clocking (SRC) scheme is proposed to solve two basic problems of the conventional resonant clocking, that is, power increase and clock waveform inability at the lower clock frequency region. The power increase prohibits widely-used dynamic frequency scaling (DFS) and the waveform instability hinders low-speed function tests. A test chip in 0.18μm CMOS is manufactured and measured to show that the SRC suppresses power increase at low clock frequency and enables the low-speed tests, while reducing the clock power by 8% at 1.5-GHz clock with an area penalty of 4.8%.

A high-speed, low-power capacitive-coupling transceiver for wireless wafer-level testing systems

Regular fabric structure is expected to reduce the process variations and increase the yield in sub-micron technology regime. Few experimental assessments, however, for the effectiveness of the regular structures has been carried out yet. In this paper, three kinds of circuit blocks are implemented with four kinds of layout styles with different regularity, and the effect of regularity on the circuit performance variations is evaluated. A test chip is fabricated with 90 nm CMOS logic process and measured results show that the regular structure increases average delay, and the worst delay of the regular structure is not better than the worst delay of normal circuits with irregular standard cells.

Switched Resonant Clocking (SRC) scheme enabling dynamic frequency scaling and low-speed test

Using capacitively coupled signaling, the feasibility of implementing an electronic connector as short as 240 mum in height is demonstrated for the first time using 0.18 mum CMOS technology and 125 mum FR4 printed circuit boards (PCBs). Maximum data rate of 500 Mbps/pin and 3.6 Gbps/mm2 are measured with 670 muW/pin of power consumption even with large parasitic capacitance associated with the FR4 board. Compared to the conventional circuits, the proposed self reset circuit can send signals 2.8x faster at the same parasitic capacitance or allow 6x more parasitic capacitance at the same data rate.

Experimental assessment of logic circuit performance variability with regular fabrics at 90nm technology node

A Through Silicon Capacitive Coupling (TSCC) interface enabling face-to-back capacitive coupling data transfer for 3D stacked dies is proposed. TSCC has three features, (1) it allows stacking more than three chips, (2) it enables easy access to the bonding pads for DC power supplies, and (3) it enables the capacitive coupling pads to be used as bonding pads. TSCC channel models are assumed and design guidelines are given for transceiver design. A transceiver designed and fabricated in 0.18μm CMOS successfully communicates through a 400μm silicon substrate at 200Mbps. It is also shown that thinning the chip will reduce the area overhead of the TSCC pad.

500Mbps, 670μW/pin capacitively coupled receiver with self reset scheme for wireless connectors

In order to reduce minimum operating voltage (VDDmin) of CMOS logic circuits, a new method reducing the within-die random threshold (VTH) variation of transistors by a post-fabrication automatically selective charge injection using substrate hot electrons (SHE) is proposed along with novel circuitry to utilize this. In the new circuit, switches are added to combinational logic circuits in order to turn them into latch loops. In order to reduce VDDmin, design guides on the optimal (1) loop topology, (2) number of stages in a loop, (3) VTH shift per charge injection, and (4) number of charge injection trials are explored through simulations. By applying the proposed scheme to 96-stage inverter chain fabricated in 65-nm CMOS, the measured reduction of VDDmin from 94mV to 74mV is successfully demonstrated for the first time.

Through Silicon Capacitive Coupling (TSCC) interface for 3D stacked dies

Clock skew is a major cause of severe timing yield degradation for sub-/near-threshold digital circuits. We report for the first time on employing hot-carrier injection (HCI) for post silicon clock-deskew trimming. An HCI trimmed clock buffer, which can be individually selected and stressed to adjust the clock edge, is proposed. In addition, it can be used in conjunction with on-chip skew monitoring circuits to achieve auto-stressing. Our approach is proven to be effective through a representative 1.1-mm × 0.8-mm clock tree in a 40-nm high-k complimentary metal-oxide-semiconductor process. On average, it reduces the clock skew by eight times at 0.4 V Vdd. No significant recovery is noticed two weeks after trimming.