Katsuyuki Machida

SiO2 planarization technology with biasing and electron cyclotron resonance plasma deposition for submicron interconnections

Bias electron cyclotron resonance (ECR) plasma deposition technology is proposed to planarize submicron interconnections with a high aspect ratio (height/space of interconnection) in which rf bias is applied to the substrate of the ECR plasma deposition system. The technology has the following advantages. First, the concave region of the narrow gap between submicron interconnections with a high aspect ratio above 1.0 can be planarized and formed at the same insulator thickness as that of the convex region. This is due to high directionality of ECR plasma particles. Second, both deposition and etching rates can be controlled by adjusting the gas flow rates as well as the rf and microwave power. Third, an rf bias can be applied from the initial stage of the planarization process. This is because of sputter‐etching with O2 ions without Ar, thus enabling a shorter planarization time. Using the bias‐ECR plasma deposition technology, the 0.5 μm line/space Al (0.5 μm thickness) interconnection surface can be per...

Novel surface structure and its fabrication process for MEMS fingerprint sensor

This paper describes a microelectromechanical systems (MEMS) fingerprint sensor that has novel protrusions on the sensor surface in order to detect clear fingerprint images for various finger surface conditions. A preliminary experiment clarified the importance of contact between soft finger ridges and the sensor surface in producing fingerprint images. Based on this, novel T-shaped protrusions on the sensor surface are proposed as an interface to mediate the contact. In order to fabricate the overhung form of the T-shaped structure, photosensitive polyimide and a copper sacrificial layer were used. Using the CMOS-compatible MEMS fabrication process, the arrayed T-shaped protrusions of polyimide are stacked on a CMOS large-scale integrated circuit. The sensor produced clear fingerprint images for various kinds of fingers. Measurement of the relationship between applied force and sensor output showed that the T-shaped protrusions achieved high sensitivity regardless of finger elasticity. Reliability tests confirmed that the sensor with the T-shaped protrusions has sufficient mechanical and electrical strength for wide applications.

Design of sub-1g microelectromechanical systems accelerometersa)

This paper presents a design of microelectromechanical systems (MEMS) accelerometers for sensing sub-1g (g = 9.8 m/s2) acceleration. The accelerometer has a high-density proof mass to suppress the Brownian noise that dominates the output noise of the sensor. The low-temperature (<400 °C) process enables to integrate the accelerometer on the sensing complementary metal-oxide semiconductor circuit by electroplating of gold; a proof mass of 1020 μm × 1020 μm in area with the thickness of 12 μm has been found to suppress the measured noise floor to 0.78 μg/Hz at 300 K, which is nearly one order of magnitude smaller than those of the conventional MEMS accelerometers made of silicon.

A novel semiconductor capacitive sensor for a single-chip fingerprint sensor/identifier LSI

We describe a new semiconductor capacitive sensor structure and the fabrication process for a single-chip fingerprint sensor/identifier LSI in which the sensor is stacked on a 0.5-/spl mu/m CMOS LSI. To ascertain the influence of the fabrication process and normal usage on the underlying LSI, sensor chips were subjected to an electrostatic discharge (ESD) test, mechanical stress test, and unsaturated pressure cooker test (USPCT). ESD tolerance is obtained at the value of /spl plusmn/3.0 kV. To investigate mechanical stress, we carried out a tapping test. The sensor is immune to mechanical stress under the condition of 10/sup 4/ taps with the strength of 1 MPa. A multilayer passivation film consisting SiN under polyimide film provides protection against contamination such as water. Thus, under USPCT conditions of 130/spl deg/C, 80% humidity, and 48 h, the chips were not degraded. The tests confirm that the proposed sensor has sufficient reliability for normal identification usage.

Capacitive-Sensing Circuit Technique for Image Quality Improvement on Fingerprint Sensor LSIs

This paper describes a new capacitive-sensing circuit technique that improves the quality of images captured with capacitive fingerprint sensor LSIs. The quality of the captured image depends on the surface condition of the finger. When the finger is dry, the electrical resistance of the finger surface is high. The finger surface resistance induces a voltage drop in the electrical potential of the finger surface (which should be grounded), which leads to poor image quality. To capture clear images even when the finger is dry, the circuit technique improves the image quality using the series resistance caused at the finger surface. The potential of the finger surface is controlled by an enhancement plate and a voltage control circuit. A test chip implementing this technique was fabricated on a 0.5 ¿m CMOS process and a sensor process. The chip captures a clear fingerprint image of a dry finger, confirming the effectiveness of the circuit technique for capturing clear fingerprint images independent of the finger surface condition with the capacitive fingerprint sensor LSIs.

Millimeter-wave photonic integrated circuit technologies for high-speed wireless communications applications

This paper describes an IC technology for high-speed wireless-link systems, using photonic techniques, which provides 10 Gb/s at 120 GHz. Optical signals are converted to electrical signals and radiated into freespace using Si-based circuitry. Both the preamp and PA utilize 0.1 /spl mu/m gate InAlAs/InGaAs HEMTs with gains of 6-10 dB and 8.5 dB, respectively.

Novel global planarization technology for interlayer dielectrics using spin on glass film transfer and hot pressing

Global planarization technology based on a new concept comprised of spin on glass (SOG) film transfer and hot pressing is proposed for interlayer dielectrics. The technology basically involves coating a SOG film onto a sheet film in advance and then transferring it from the sheet film to a Si substrate by pressing and heating it in a vacuum. Planarization and filling of the interlayer dielectrics can be carried out by this process. For this technology, perhydrosilazane, which has a high viscosity for a thick formation during coating and a low viscosity for the flow during heating, is used as the SOG material. Experimental results show that the SOG thickness is reduced by the pressing and heating process and that its uniformity can be improved by the press force. By applying this technology to Al interconnection, it is found that planarization and filling can be completely realized. Therefore, this technology is very promising for simple and inexpensive global planarization.

RF CMOS-MEMS Switch with Low-Voltage Operation for Single-Chip RF LSIs

This paper describes a novel RF CMOS-MEMS switch that integrates RF MEMS switches and CMOS control circuits. A single-pole 8-through RF CMOS-MEMS switch was fabricated and its operation at 3.3 V supply voltage was achieved. The switch was encapsulated with a thin film at wafer level to prevent destruction during packaging. Experimental results confirm that the switch has mechanical reliability for more than 1 billion cycles

A pixel-level automatic calibration circuit scheme for capacitive fingerprint sensor LSIs

We propose a pixel-level automatic calibration circuit scheme that initializes a capacitive fingerprint sensor LSI to eliminate the influence of the surface condition, which is degraded by dirt during long-time use. The scheme consists of an automatic calibration circuit for each pixel and a calibration control circuit for the pixel array. The calibration is executed by adjusting variable capacitance in each pixel to make the sensor signals of all pixels the same. The calibration control circuit selects the pixels in parallel, and calibrates all pixels in a short time. The scheme was applied to a fingerprint sensor LSI using the 0.5-/spl mu/m CMOS process/sensor process, and clear fingerprint images were obtained even for a degraded surface condition. This confirms that the scheme is effective for capturing consistent clear images during long-time use.

A new sensor structure and fabrication process for a single-chip fingerprint sensor/identifier LSI

We propose a new sensor structure and the fabrication process for a single-chip fingerprint sensor/identifier LSI in which the sensor is stacked on a 0.5 /spl mu/m CMOS LSI. We investigate the influence of electrostatic discharge (ESD), mechanical stress, and water penetration on the sensors reliability. The results reveal ESD tolerance is obtained at the value of 2.0 kV, the sensor is immune to mechanical stress under the condition of 1 MPa tapping tests, and it is protected against contamination by a passivation film. The tests confirm that the sensor has sufficient reliability for conventional identification usage.