Katsuyuki Yonehara

Competitiveness and Technical Challenges of Low Cost Wirebond Packaging for High Speed SerDes Applications in ASICs

This paper discusses the challenges in balancing the wireability, performance, and cost of low cost wirebond packaging for high speed SerDes applications in application specific integrated circuits (ASICs). In-depth analysis was performed using 3D electromagnetic simulation to evaluate the effect on performance of various design factors along the signal path of the wirebond package, including bondwire, microstrip, and ball grid array (BGA) assignment. The tradeoff between wireability and performance of these design factors is discussed. Hardware measurements were performed on a functioning high speed SerDes test site which was designed to optimize wireability for the application while still achieving performance well beyond the 3 gigabits per second (Gbps) data rate for which it was designed. Projections are made concerning design variables that can be adjusted to meet the requirements of wire count, package size, and performance, enabling the ability to design for a broad application space in high speed SerDes applications.

Common Mode Return Loss Consideration in Wirebond Packaging for High Speed SerDes Links

This paper discusses the trade-offs in performance and cost of high speed SerDes in wirebond package applications. While many protocol standards specify requirements for both common mode return loss and differential mode return loss, meeting both sets of requirements in low cost wirebond packages requires the designer to make significant trade-offs. The performance and cost impacts of improving common mode return loss in wirebond packaging is examined from several different points of view

Consideration of chip circuit damage on DCS-FBGA packages

Laminate type FBGA package is one of the advanced solutions of economic chip scale package, effective for applications that require low profile and small area as cellular phones or hand held products. IBM stared to use an advanced package, DCS (Dual Chip Stacked)-FBGA, to obtain higher communication rate between dual semiconductor chips into one package, which were originally placed on different packages on wider space cards. During the development stage two subjects were concerned as, damage on the bottom-chip circuits under the top-chip placement region, and the reliability impacts. The top and bottom chip size combination in DCS-FBGA has a large difference ratio comparing to memory chips stack type packages, which is applied widely in the industry. Assessment studies on different CTE materials, chip thickness, construction, attachment methods, and reliability performances were analyzed. The result was validated by experiments to monitor the contact resistance discrepancy on the chip. To minimize these impacts, we confirmed the correlation between chip attach technique and mechanical reliability. This paper contains details of the phenomenon, solutions and effectiveness.