nju Na

The effects of on-chip and package decoupling capacitors and an efficient ASIC decoupling methodology

This paper presents an in-depth analysis of the effectiveness of on-chip and package decoupling capacitors in light of the interaction between chip-package resonance and the frequency content of switching sources, and suggests an approach for decoupling analysis in fast turn-around ASIC designs, achieving both simulation efficiency and accuracy. The analysis is based on accurate modeling of the on-chip and package power supply structures of ASIC flip-chip modules as distributed networks to provide precise understanding of switching noise mechanisms in distributed power supply structures in both the time and frequency domains. The simulation efficiency versus accuracy of two types of package models is discussed. The local effectiveness of on-chip and package decoupling capacitors is illustrated using detailed, frequency-domain impedance profiles of the on-chip and package power supply networks, demonstrating location-dependant responses that vary according to the local placement of decoupling capacitors. Based on the study, a methodology is presented for accurately determining the quantities and locations of on-chip decoupling capacitors required to limit on-chip transient power supply collapse to a pre-defined level.

Design optimization for isolation in high wiring density packages with high speed SerDes links

This paper discusses design tradeoffs for high speed signal performance in buildup laminate packages with high wiring density. Trace design in die escaping area, PTH vias placement pattern and BGA I/O assignments are analyzed in depth for design optimization through numerous simulations as major areas of high coupling concern and channel performance. Then design suggestions are made at each area for performance and cost optimization and design strategies are developed to achieve the overall required performance as a whole system. Lastly some coupling test results on HSS links are presented to verify the performance of the design

Link analysis and design of high speed storage buses in backplane and cabling environments

This paper discusses electrical performance and design aspects of SAS (Serial Attached SCSI) link channels in various server storage system configurations through modeling and simulation analysis in frequency and time domain. The signal loss behaviors are investigated in two interconnect structures, internal SAS links in host enclosure backplanes and external SAS links in cabling environment. While signals in external SAS links experience excessive loss through lengthy cables in meters, those of internal SAS links are impaired by multiple discontinuities of board components over less than a couple of feet of PCB routing though largely dependent of system design. While eye closure is parallel to loss magnitude in general, higher degree of discontinuities exhibited in frequency loss behavior of channels result in more eye closure despite lower loss magnitude reducing design space budget and the impact is greater with higher data rates.

Competitiveness and Technical Challenges of Low Cost Wirebond Packaging for High Speed SerDes Applications in ASICs

This paper discusses the challenges in balancing the wireability, performance, and cost of low cost wirebond packaging for high speed SerDes applications in application specific integrated circuits (ASICs). In-depth analysis was performed using 3D electromagnetic simulation to evaluate the effect on performance of various design factors along the signal path of the wirebond package, including bondwire, microstrip, and ball grid array (BGA) assignment. The tradeoff between wireability and performance of these design factors is discussed. Hardware measurements were performed on a functioning high speed SerDes test site which was designed to optimize wireability for the application while still achieving performance well beyond the 3 gigabits per second (Gbps) data rate for which it was designed. Projections are made concerning design variables that can be adjusted to meet the requirements of wire count, package size, and performance, enabling the ability to design for a broad application space in high speed SerDes applications.

DC wander effect of DC blocking capacitors on PCIe Gen3 signal integrity

This paper discusses the impact of DC wander also called baseline wander resulting from AC-coupling on signal integrity in receive waveforms in AC-coupled serial bus links with focus on PCIe Gen3 signaling. Receive signal behavior from charging and discharging activities of AC-coupling circuit is studied for fundamental understanding of baseline wander and its effect through simulations of short and long channels from various aspects of PCIe Gen3 signaling and high speed serial links in general.

ASIC packaging challenges with high speed interfaces

Networking speed is exploding as demanded with technology advancements and industry chip technology is evolving with rapidly increasing serial link data rates with high link integration for higher aggregate bandwidth and shrinking chip area and interface dimensions of devices. However, a large development speed gap between chip technologies and package technologies places great packaging challenges for high speed link applications where package wireability is driven by high frequency performance requirements. This paper discusses packaging challenges of high speed link applications with cost-performance tradeoffs in the technology trend.

High frequency loss characterization of FCPBGA package materials with humidity and temperature variation

As electronic device modules are operated in varying temperature and humidity conditions over cycles, package substrates experience material property changes including electrical characteristics in different environment conditions with electrical performance affected in particular at high frequencies. This paper presents temperature and moisture effect on electrical performance of high speed interconnects through raw material characterization and high frequency loss measurements on package interconnect. Measurements on raw material and differential test conductor structures show a great loss dependence on temperature and moisture with a significant loss increase in higher temperature and moisture condition at high frequencies The paper also discusses package loss budget to application space relation taking into account those effects in high speed designs.

Driver design for DDR4 memory subsystems

As DDR4 continues to move from the design phase towards implementation, several challenges have been identified to successfully implement this high performance memory architecture for next generation systems. This paper investigates driver design selection for DDR4 systems. The paper studies the pros and cons of three driver design types namely: standard, pre-emphasis, and de-emphasis on typical net topogies of 1DPC (DIMM per channel) and 2DPC operated at 2400MT/s. For each driver type the impact of source termination on performance and power saving capability is discussed. Since the effects associated with different driver designs can be best understood in the time domain this paper uses behavioral models created in the SPICE format for simulations.

Common Mode Return Loss Consideration in Wirebond Packaging for High Speed SerDes Links

This paper discusses the trade-offs in performance and cost of high speed SerDes in wirebond package applications. While many protocol standards specify requirements for both common mode return loss and differential mode return loss, meeting both sets of requirements in low cost wirebond packages requires the designer to make significant trade-offs. The performance and cost impacts of improving common mode return loss in wirebond packaging is examined from several different points of view

PCIe Gen3 link design and tuning in server systems with end devices from multiple IP suppliers

This paper discusses link routing budget considerations for PCIe Gen3 designs in server systems. Special attention will be given to channel discontinuities and their effect on eye opening. Link training complications will be discussed with respect to equalization and tuning behavior when accommodating multiple transmitters and receivers from different vendor sources. Insertion loss plots and eye simulation data will be analyzed and interpreted. Hardware data will show that optimally simulated equalization cases may not necessarily occur.